Microchip Technology DM240015 Data Sheet
2012-2013 Microchip Technology Inc.
DS30009312B-page 157
PIC24FJ128GC010 FAMILY
REGISTER 8-46:
INTTREG: INTERRUPT CONTROLLER TEST REGISTER
R-0
r-0
R/W-0
U-0
R-0
R-0
R-0
R-0
CPUIRQ
r
VHOLD
—
ILR3
ILR2
ILR1
ILR0
bit 15
bit 8
U-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
—
VECNUM6
VECNUM5
VECNUM4
VECNUM3
VECNUM2
VECNUM1
VECNUM0
bit 7
bit 0
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CPUIRQ:
Interrupt Request from Interrupt Controller CPU bit
1
= An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens
when the CPU priority is higher than the interrupt priority
0
= No interrupt request is unacknowledged
bit 14
Reserved:
Maintain as ‘0’
bit 13
VHOLD:
Vector Number Capture Configuration bit
1
= VECNUM<6:0> contain the value of the highest priority pending interrupt
0
= VECNUM<6:0> contain the value of the last Acknowledged interrupt (i.e., the last interrupt that has
occurred with higher priority than the CPU, even if other interrupts are pending)
bit 12
Unimplemented:
Read as ‘0’
bit 11-8
ILR<3:0>:
New CPU Interrupt Priority Level bits
1111
= CPU Interrupt Priority Level is 15
•
•
•
0001
•
•
0001
= CPU Interrupt Priority Level is 1
0000
= CPU Interrupt Priority Level is 0
bit 7
Unimplemented:
Read as ‘0’
bit 6-0
VECNUM<6:0>:
Vector Number of Pending Interrupt or Last Acknowledged Interrupt bits
When VHOLD = 1:
Indicates the vector number (from 0 to 118) of the last interrupt to occur.
When VHOLD = 0:
Indicates the vector number (from 0 to 118) of the interrupt request currently being handled.
Indicates the vector number (from 0 to 118) of the last interrupt to occur.
When VHOLD = 0:
Indicates the vector number (from 0 to 118) of the interrupt request currently being handled.