Microchip Technology DM240015 Data Sheet
PIC24FJ128GC010 FAMILY
DS30009312B-page 280
2012-2013 Microchip Technology Inc.
19.7
USB OTG Module Registers
There are a total of 37 memory mapped registers asso-
ciated with the USB OTG module. They can be divided
into four general categories:
• USB OTG Module Control (12)
• USB Interrupt (7)
• USB Endpoint Management (16)
• USB V
ciated with the USB OTG module. They can be divided
into four general categories:
• USB OTG Module Control (12)
• USB Interrupt (7)
• USB Endpoint Management (16)
• USB V
BUS
Power Control (2)
This total does not include the (up to) 128 BD registers
in the BDT. Their prototypes, described in
in the BDT. Their prototypes, described in
and
, are shown separately in
.
All USB OTG registers are implemented in the Least
Significant Byte (LSB) of the register. Bits in the upper
byte are unimplemented and have no function. Note
that some registers are instantiated only in Host mode,
while other registers have different bit instantiations
and functions in Device and Host modes.
The registers described in the following sections are
those that have bits with specific control and configura-
tion features. The following registers are used for data
or address values only:
• U1BDTP1: Specifies the 256-word page in data
Significant Byte (LSB) of the register. Bits in the upper
byte are unimplemented and have no function. Note
that some registers are instantiated only in Host mode,
while other registers have different bit instantiations
and functions in Device and Host modes.
The registers described in the following sections are
those that have bits with specific control and configura-
tion features. The following registers are used for data
or address values only:
• U1BDTP1: Specifies the 256-word page in data
RAM used for the BDT; 8-bit value with bit 0 fixed
as ‘0’ for boundary alignment.
as ‘0’ for boundary alignment.
• U1FRML and U1FRMH: Contain the 11-bit byte
counter for the current data frame.