Microchip Technology DM240015 Data Sheet
PIC24FJ128GC010 FAMILY
DS30009312B-page 360
2012-2013 Microchip Technology Inc.
REGISTER 26-9:
ADLnPTR: A/D SAMPLE LIST n POINTER REGISTER (n = 0 to 3)
U-0
R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC
R/W-0
R/W-0
R/W-0
—
ADNEXT6
ADNEXT5
ADNEXT4
ADNEXT3
ADNEXT2
ADNEXT1
ADNEXT0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented:
Read as ‘0’
bit 14-8
ADNEXT<6:0>:
Pointer to Next Entry on Sample List to be Converted bits
This value is added to the start of the sample list to determine the ADTBLn register to be used for the
next trigger event.
next trigger event.
bit 7-0
Unimplemented:
Read as ‘0’
REGISTER 26-10: ADTBLn: A/D SAMPLE TABLE ENTRY n REGISTER (n = 0 to 31)
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
UCTMU
DIFF
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
ADCH6
ADCH5
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
UCTMU:
Enable CTMU During Entry Conversion bit
1
= CTMU is enabled during channel conversion for this entry
0
= CTMU is disabled during channel conversion for this entry
bit 14
DIFF:
Differential Inputs Select bit
1
= Analog inputs are sampled as differential pairs for this entry
0
= Analog inputs are sampled as single-ended for this entry
bit 13-7
Unimplemented:
Read as ‘0’
bit 6-0
ADCH<6:0>:
A/D Channel Entry Select bits
for a complete description.