Microchip Technology DM240015 Data Sheet
PIC24FJ128GC010 FAMILY
DS30009312B-page 406
2012-2013 Microchip Technology Inc.
REGISTER 34-4:
CW4: FLASH CONFIGURATION WORD 4
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
IOL1WAY
I2C2SEL
PLLDIV3
PLLDIV2
PLLDIV1
PLLDIV0
RTCBAT
DSSWEN
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
DSWDTEN
DSBOREN
DSWDTOSC
DSWDPS4
DSWDPS3
DSWDPS2
DSWDPS1
DSWDPS0
bit 7
bit 0
Legend:
PO = Program Once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-16
Unimplemented:
Read as ‘1’
bit 15
IOL1WAY:
IOLOCK One-Way Set Enable bit
1
= The IOLOCK bit (OSCCON<6>) can be set once, provided the unlock sequence has been
completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.
0
= The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been
completed
bit 14
I2C2SEL:
Alternate I2C2 Location Select bit
For PIC24FJXXXGC010 Devices:
1
1
= I2C2 functions; SCL2 and SDA2 are mapped to RA2 and RA3, respectively
0
= I2C2 functions; SCL2 and SDA2 are mapped to RF5 and RF4, respectively
For PIC24FJXXXGC006 Devices:
Reserved, maintain as ‘1’.
Reserved, maintain as ‘1’.
bit 13-10
PLLDIV<3:0:>
USB 96 MHz PLL Prescaler Select bits
1111
= PLL disabled
1110
....
= Reserved, do not use
1000
0111
= Oscillator input divided by 12 (48 MHz input)
0110
= Oscillator input divided by 8 (32 MHz input)
0101
= Oscillator input divided by 6 (24 MHz input)
0100
= Oscillator input divided by 5 (20 MHz input)
0011
= Oscillator input divided by 4 (16 MHz input)
0010
= Oscillator input divided by 3 (12 MHz input)
0001
= Oscillator input divided by 2 (8 MHz input)
0000
= Oscillator input used directly (4 MHz input)
bit 9
RTCBAT:
V
BAT
RTCC Operation Select bit
1
= RTCC operation continues when the device is in V
BAT
mode
0
= RTCC operation stops when the device is in V
BAT
mode
bit 8
DSSWEN:
Deep Sleep Software Control Select bit
1
= Deep Sleep operation is enabled and controlled by the DSEN bit
0
= Deep Sleep operation is disabled
bit 7
DSWDTEN:
Deep Sleep Watchdog Timer Enable bit
1
= Deep Sleep WDT is enabled
0
= Deep Sleep WDT is disabled