Microchip Technology DM240015 Data Sheet
2012-2013 Microchip Technology Inc.
DS30009312B-page 417
PIC24FJ128GC010 FAMILY
36.0
INSTRUCTION SET SUMMARY
The PIC24F instruction set adds many enhancements
to the previous PIC
to the previous PIC
®
MCU instruction sets, while main-
taining an easy migration from previous PIC MCU
instruction sets. Most instructions are a single program
memory word. Only three instructions require two
program memory locations.
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction. The instruction set is
highly orthogonal and is grouped into four basic
categories:
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations
instruction sets. Most instructions are a single program
memory word. Only three instructions require two
program memory locations.
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction. The instruction set is
highly orthogonal and is grouped into four basic
categories:
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations
shows the general symbols used in
describing the instructions. The PIC24F instruction set
summary in
summary in
lists all the instructions, along
with the status flags affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand, which is typically a
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand, which is typically a
register, ‘Wb’, without any address modifier
• The second source operand, which is typically a
register, ‘Ws’, with or without an address modifier
• The destination of the result, which is typically a
register, ‘Wd’, with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value, ‘f’
• The destination, which could either be the file
have two operands:
• The file register specified by the value, ‘f’
• The destination, which could either be the file
register, ‘f’, or the W0 register, which is denoted
as ‘WREG’
as ‘WREG’
Most bit-oriented instructions (including simple
rotate/shift instructions) have two operands:
• The W register (with or without an address
rotate/shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
‘Ws’ or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register, ‘Wb’)
contents of register, ‘Wb’)
The literal instructions that involve data movement may
use some of the following operands:
• A literal value to be loaded into a W register or file
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by the value of ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register, ‘Wb’,
logical operations use some of the following operands:
• The first source operand, which is a register, ‘Wb’,
without any address modifier
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register, ‘Wd’, with or without an address modifier
register, ‘Wd’, with or without an address modifier
The control instructions may use some of the following
operands:
• A program memory address
• The mode of the table read and table write
operands:
• A program memory address
• The mode of the table read and table write
instructions
All instructions are a single word, except for certain
double-word instructions, which were made
double-word instructions so that all the required infor-
mation is available in these 48 bits. In the second word,
the 8 MSbs are ‘0’s. If this second word is executed as
an instruction (by itself), it will execute as a NOP.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (uncondi-
tional/computed branch), indirect CALL/GOTO, all table
reads and writes, and RETURN/RETFIE instructions,
which are single-word instructions but take two or three
cycles.
Certain instructions that involve skipping over the sub-
sequent instruction require either two or three cycles if
the skip is performed, depending on whether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves require two
cycles. The double-word instructions execute in two
instruction cycles.
double-word instructions, which were made
double-word instructions so that all the required infor-
mation is available in these 48 bits. In the second word,
the 8 MSbs are ‘0’s. If this second word is executed as
an instruction (by itself), it will execute as a NOP.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (uncondi-
tional/computed branch), indirect CALL/GOTO, all table
reads and writes, and RETURN/RETFIE instructions,
which are single-word instructions but take two or three
cycles.
Certain instructions that involve skipping over the sub-
sequent instruction require either two or three cycles if
the skip is performed, depending on whether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves require two
cycles. The double-word instructions execute in two
instruction cycles.
Note:
This chapter is a brief summary of the
PIC24F Instruction Set Architecture (ISA)
and is not intended to be a comprehensive
reference source.
PIC24F Instruction Set Architecture (ISA)
and is not intended to be a comprehensive
reference source.