Microchip Technology DM240015 Data Sheet
2012-2
013 M
ic
rochip
T
e
chnology
In
c.
DS
30009312B
30009312B
-page 73
PIC24FJ128GC010 FAMILY
TABLE 4-37:
DEEP SLEEP REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
DSCON
0758
DSEN
—
—
—
—
—
—
—
—
—
—
—
—
r
DSBOR
RELEASE 0000
)
DSWAKE
075A
—
—
—
—
—
—
—
DSINT0
DSFLT
—
—
DSWDT DSRTCC DSMCLR
—
—
0000
)
DSGPR0
075C
Deep Sleep Semaphore Data 0
0000
)
DSGPR1
075E
Deep Sleep Semaphore Data 1
0000
)
Legend:
— = unimplemented, read as ‘0’; r = reserved. Reset values are shown in hexadecimal.
Note 1:
These registers are only reset on a V
DD
POR event.
TABLE 4-38:
NVM REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
NVMCON
0760
WR
WREN
WRERR
—
—
—
—
—
—
ERASE
—
—
NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000
(
NVMKEY
0766
—
—
—
—
—
—
—
—
NVMKEY Register<7:0>
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
The Reset value shown is for POR only. The value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-39:
PMD REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PMD1
0770
T5MD
T4MD
T3MD
T2MD
T1MD
—
—
—
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
—
—
ADC1MD
0000
PMD2
0772
IC8MD
IC7MD
IC6MD
IC5MD
IC4MD
IC3MD
IC2MD
IC1MD
OC8MD
OC7MD
OC6MD
OC5MD
OC4MD
OC3MD
OC2MD
OC1MD
0000
PMD3
0774
—
—
—
—
TXMMD
CMPMD RTCCMD
PMPMD
CRCMD
DAC1MD
—
—
U3MD
—
I2C2MD
—
0000
PMD4
0776
—
—
—
—
—
—
—
—
—
UPWMMD
U4MD
—
REFOMD CTMUMD HLVDMD USB1MD
0000
PMD5
0778
—
—
—
—
—
—
—
IC9MD
—
—
—
—
—
—
—
OC9MD
0000
PMD6
077A
—
—
—
—
—
—
—
—
—
LCDMD
AMP1MD DAC2MD AMP2MD SDA1MD
—
—
0000
PMD7
077C
—
—
—
—
—
—
—
—
—
—
DMA1MD DMA0MD
—
—
—
—
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.