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Microchip Technology DM240015 Data Sheet

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PIC24FJ128GC010 FAMILY
DS30009312B-page 98
 
 2012-2013 Microchip Technology Inc.
REGISTER 7-1:
RCON: RESET CONTROL REGISTER
R/W-0
R/W-0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
TRAPR
(
)
IOPUWR
—
RETEN
—
DPSLP
)
CM
(
)
PMSLP
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
EXTR
(
SWR
SWDTEN
)
WDTO
(
)
SLEEP
IDLE
BOR
POR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TRAPR:
 Trap Reset Flag bit
(
)
1
 = A Trap Conflict Reset has occurred
0
 = A Trap Conflict Reset has not occurred
bit 14
IOPUWR:
 Illegal Opcode or Uninitialized W Access Reset Flag bit
(
)
1
 = An illegal opcode detection, an illegal address mode or Uninitialized W register is used as an
Address Pointer and caused a Reset
0
 = An illegal opcode or Uninitialized W Reset has not occurred
bit 13
Unimplemented:
 Read as ‘0’
bit 12
RETEN:
 Retention Mode Enable bit
)
1
 = Retention mode is enabled while device is in Sleep modes (1.2V regulator supplies to the core)
0
 = Retention mode is disabled; normal voltage levels are present
bit 11
Unimplemented:
 Read as ‘0’
bit 10
DPSLP: 
Deep Sleep Flag bit
(
)
1
 = Device has been in Deep Sleep mode
0
 = Device has not been in Deep Sleep mode
bit 9
CM:
 Configuration Word Mismatch Reset Flag bit
1
 = A Configuration Word Mismatch Reset has occurred
0
 = A Configuration Word Mismatch Reset has not occurred
bit 8
PMSLP:
 Program Memory Power During Sleep bit
(
1
 = Program memory bias voltage remains powered during Sleep 
0
 = Program memory bias voltage is powered down during Sleep 
bit 7
EXTR:
 External Reset (MCLR) Pin bit
(
)
1
 = A Master Clear (pin) Reset has occurred
0
 = A Master Clear (pin) Reset has not occurred
bit 6
SWR:
 Software Reset (Instruction) Flag bit
(
)
1
  = A  RESET instruction has been executed
0
  = A  RESET instruction has not been executed
Note 1:
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not 
cause a device Reset.
2:
If the LPCFG Configuration bit is ‘1’ (unprogrammed), the retention regulator is disabled and the RETEN 
bit has no effect.
3:
Re-enabling the regulator after it enters Standby mode will add a delay, T
VREG
, when waking up from 
Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from 
occurring.
4:
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the 
SWDTEN bit setting.