Microchip Technology MA330020 Data Sheet

Page of 398
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70000318G-page 18
 2008-2014 Microchip Technology Inc.
FIGURE 1-1:
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 BLOCK DIAGRAM       
 16
OSC1/CLKI
OSC2/CLKO
V
DD
, V
SS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
FRC/LPRC
Oscillators
Regulator
Voltage
V
CAP
IC1
I2C1
PORTA
Instruction
Decode &
Control
PCH
16
Program Counter
23
23
24
23
PCU
16 x 16
W Register Array
ROM Latch
16
 16
 16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Address Latch
Program Memory
Data Latch
  
   
L
ite
ra
l D
a
ta
 16
 16
16
 16
Data Latch
Address
Latch
16
X RAM
16
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
Control Signals
to Various Blocks
ADC1
Timers
PORTB
Address Generator Units
1-3
CNx
UART1
PWM
4 x 2
Remappable
Pins
PORTC
SPI1
OC1
OC2
Analog
Comparators 1-4
Note:
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and
features present on each device.
PCL
Data Latch
Address
Latch
Y RAM
EA MUX
Instruction Reg
16-Bit ALU
IC2