Microchip Technology MA330020 Data Sheet
2008-2014 Microchip Technology Inc.
DS70000318G-page 213
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
bit 3-2
CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMODE is Enabled bits
(
)
FCLCONx<IFLTMOD> = 0: Normal Fault mode:
If current-limit is active, then CLDAT<1> provides the state for PWMxH
If current-limit is active, then CLDAT<0> provides the state for PWMxL
If current-limit is active, then CLDAT<1> provides the state for PWMxH
If current-limit is active, then CLDAT<0> provides the state for PWMxL
FCLCONx<IFLTMOD> = 1: Independent Fault mode:
CLDAT<1:0> bits are ignored.
CLDAT<1:0> bits are ignored.
bit 1
SWAP<1:0>: Swap PWMxH and PWMxL pins
1
= PWMxH output signal is connected to the PWMxL pin and the PWMxL signal is connected to the
PWMxH pins
0
= PWMxH and PWMxL pins are mapped to their respective pins
bit 0
OSYNC: Output Override Synchronization bit
1
= Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base
0
= Output overrides via the OVDDAT<1:0> bits occur on the next CPU clock boundary
REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER (CONTINUED)
Note 1:
These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
yield unpredictable results.
2:
The state represents the active/inactive state of the PWM module depending on the POLH and POLL bit
settings.
settings.