Microchip Technology MA330020 Data Sheet
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70000318G-page 38
2008-2014 Microchip Technology Inc.
3.5
Arithmetic Logic Unit (ALU)
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 ALU is 16 bits wide and is capable of addition,
subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are 2’s com-
plement in nature. Depending on the operation, the ALU
can affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC) Status
bits in the SR register. The C and DC Status bits operate
as Borrow and Digit Borrow bits, respectively, for
subtraction operations.
X04 ALU is 16 bits wide and is capable of addition,
subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are 2’s com-
plement in nature. Depending on the operation, the ALU
can affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC) Status
bits in the SR register. The C and DC Status bits operate
as Borrow and Digit Borrow bits, respectively, for
subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
Refer to the “16-bit MCU and DSC Programmer’s
Reference Manual” (DS70157) for information on the
SR bits affected by each instruction.
Reference Manual” (DS70157) for information on the
SR bits affected by each instruction.
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 CPU incorporates hardware support for both multipli-
cation and division. This includes a dedicated hardware
multiplier and support hardware for 16-bit-divisor division.
X04 CPU incorporates hardware support for both multipli-
cation and division. This includes a dedicated hardware
multiplier and support hardware for 16-bit-divisor division.
3.5.1
MULTIPLIER
Using the high-speed, 17-bit x 17-bit multiplier of the
DSP engine, the ALU supports unsigned, signed or
mixed sign operation in several MCU multiplication
modes:
DSP engine, the ALU supports unsigned, signed or
mixed sign operation in several MCU multiplication
modes:
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
3.5.2
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
signed and unsigned integer divide operations with the
following data sizes:
• 32-bit signed/16-bit signed divide
• 32-bit unsigned/16-bit unsigned divide
• 16-bit signed/16-bit signed divide
• 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0 and
the remainder in W1. The 16-bit signed and unsigned
DIV
the remainder in W1. The 16-bit signed and unsigned
DIV
instructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both 32-bit/
16-bit and 16-bit/16-bit instructions take the same
number of cycles to execute.
(W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both 32-bit/
16-bit and 16-bit/16-bit instructions take the same
number of cycles to execute.
3.6
DSP Engine
The DSP engine consists of a high-speed, 17-bit x 17-bit
multiplier, a barrel shifter and a 40-bit adder/subtracter
(with two target accumulators, round and saturation
logic).
multiplier, a barrel shifter and a 40-bit adder/subtracter
(with two target accumulators, round and saturation
logic).
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 is a single-cycle instruction flow architecture;
therefore, concurrent operation of the DSP engine with
MCU instruction flow is not possible. However, some
MCU ALU and DSP engine resources can be used
concurrently by the same instruction (for example, ED,
EDAC
X04 is a single-cycle instruction flow architecture;
therefore, concurrent operation of the DSP engine with
MCU instruction flow is not possible. However, some
MCU ALU and DSP engine resources can be used
concurrently by the same instruction (for example, ED,
EDAC
).
The DSP engine can also perform inherent
accumulator-to-accumulator operations that require no
additional data. These instructions are ADD, SUB and
NEG
accumulator-to-accumulator operations that require no
additional data. These instructions are ADD, SUB and
NEG
.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
the CPU Core Control register (CORCON), as listed
below:
• Fractional or Integer DSP Multiply (IF)
• Signed or Unsigned DSP Multiply (US)
• Conventional or Convergent Rounding (RND)
• Automatic Saturation On/Off for ACCA (SATA)
• Automatic Saturation On/Off for ACCB (SATB)
• Automatic Saturation On/Off for Writes to Data
Memory (SATDW)
• Accumulator Saturation mode Selection
(ACCSAT)
A block diagram of the DSP engine is shown in
TABLE 3-1:
DSP INSTRUCTIONS
SUMMARY
SUMMARY
Instruction
Algebraic
Operation
ACC
Write Back
CLR
A = 0
Yes
ED
A = (x – y)
2
No
EDAC
A = A + (x – y)
2
No
MAC
A = A + (x * y)
Yes
MAC
A = A + x
2
No
MOVSAC
No change in A
Yes
MPY
A = x * y
No
MPY
A = x
2
No
MPY.N
A = – x * y
No
MSC
A = A – x * y
Yes