Microchip Technology AC164112 Data Sheet
© 2009 Microchip Technology Inc.
DS41341E-page 111
PIC16F72X/PIC16LF72X
11.0
TIMER0 MODULE
The Timer0 module is an 8-bit timer/counter with the
following features:
following features:
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (shared with Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
• TMR0 can be used to gate Timer1
Figure 11-1 is a block diagram of the Timer0 module.
11.1
Timer0 Operation
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
or an 8-bit counter.
11.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-Bit Timer mode is
selected by clearing the T0CS bit of the OPTION
register.
cycle, if used without a prescaler. 8-Bit Timer mode is
selected by clearing the T0CS bit of the OPTION
register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
two instruction cycles immediately following the write.
11.1.2
8-BIT COUNTER MODE
In 8-Bit Counter mode, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin or the Capacitive Sensing Oscillator (CPSOSC)
signal.
increment on every rising or falling edge of the T0CKI
pin or the Capacitive Sensing Oscillator (CPSOSC)
signal.
8-Bit Counter Mode using the T0CKI pin is selected by
setting the T0CS bit in the OPTION register to ‘1’ and
resetting the T0XCS bit in the CPSCON0 register to ‘0’.
setting the T0CS bit in the OPTION register to ‘1’ and
resetting the T0XCS bit in the CPSCON0 register to ‘0’.
8-Bit Counter Mode using the Capacitive Sensing
Oscillator (CPSOSC) signal is selected by setting the
T0CS bit in the OPTION register to ‘1’ and setting the
T0XCS bit in the CPSCON0 register to ‘1’.
Oscillator (CPSOSC) signal is selected by setting the
T0CS bit in the OPTION register to ‘1’ and setting the
T0XCS bit in the CPSCON0 register to ‘1’.
The rising or falling transition of the incrementing edge
for either input source is determined by the T0SE bit in
the OPTION register.
for either input source is determined by the T0SE bit in
the OPTION register.
FIGURE 11-1:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Note:
The value written to the TMR0 register can
be adjusted, in order to account for the two
instruction cycle delay when TMR0 is
written.
be adjusted, in order to account for the two
instruction cycle delay when TMR0 is
written.
T0CKI
T0SE
TMR0
WDT
Time-out
PS<2:0>
WDTE
Data Bus
Set Flag bit T0IF
on Overflow
T0CS
0
1
0
1
0
1
8
8
8-bit
Prescaler
0
1
F
OSC
/4
PSA
PSA
PSA
Sync
2 T
CY
Overflow to Timer1
Divide by
512
TMR1GE
T1GSS = 11
1
0
Cap. Sensing
T0XCS
Oscillator
Low-Power
WDT OSC
WDT OSC