Microchip Technology AC164112 Data Sheet

© 2009 Microchip Technology Inc.

DS41341E-page 43

The PIC16F72X/PIC16LF72X device family features
an interruptible core, allowing certain events to
preempt normal program flow. An Interrupt Service
Routine (ISR) is used to determine the source of the
interrupt and act accordingly. Some interrupts can be
configured to wake the MCU from Sleep mode.

The PIC16F72X/PIC16LF72X device family has 12
interrupt sources, differentiated by corresponding
interrupt enable and flag bits:

• Timer0 Overflow Interrupt

• External Edge Detect on INT Pin Interrupt

• PORTB Change Interrupt

• Timer1 Gate Interrupt

• A/D Conversion Complete Interrupt

• AUSART Receive Interrupt

• AUSART Transmit Interrupt

• SSP Event Interrupt

• CCP1 Event Interrupt

• Timer2 Match with PR2 Interrupt

• Timer1 Overflow Interrupt

• CCP2 Event Interrupt

A block diagram of the interrupt logic is shown in
Figure 4-1.

T0IF
T0IE

INTF
INTE
RBIF

RBIE

GIE

PEIE

Wake-up (If in Sleep mode)

Interrupt to CPU

TMR1GIE

TMR1GIF

ADIF
ADIE

IOC-RB0

IOCB0

IOC-RB1

IOCB1

IOC-RB2

IOCB2

IOC-RB3

IOCB3

CCP1IF
CCP1IE

IOC-RB4

IOCB4

IOC-RB5

IOCB5

IOC-RB6

IOCB6

IOC-RB7

IOCB7

RCIF

RCIE

TMR2IE

TMR2IF

SSPIE

SSPIF

TXIE

TXIF

TMR1IE

TMR1IF

Some peripherals depend upon the 
system clock for operation. Since the 
system clock is suspended during 
Sleep, these peripherals will not wake 
the part from Sleep. See Section 19.1 
“Wake-up from Sleep”.

CCP2IF
CCP2IE