Microchip Technology DM183021 Data Sheet
2010 Microchip Technology Inc.
DS39616D-page 113
PIC18F2331/2431/4331/4431
11.0
I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Data Latch)
The Data Latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
A simplified model of a generic I/O port without the
interfaces to other peripherals is shown in
The Data Latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
A simplified model of a generic I/O port without the
interfaces to other peripherals is shown in
FIGURE 11-1:
GENERIC I/O PORT
OPERATION
OPERATION
11.1
PORTA, TRISA and LATA
Registers
Registers
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The Data Latch register (LATA) is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
The RA<4:2> pins are multiplexed with three input
capture pins and Quadrature Encoder Interface pins.
Pins, RA6 and RA7, are multiplexed with the main
oscillator pins. They are enabled as oscillator or I/O
pins by the selection of the main oscillator in
Configuration Register 1H (see
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The Data Latch register (LATA) is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
The RA<4:2> pins are multiplexed with three input
capture pins and Quadrature Encoder Interface pins.
Pins, RA6 and RA7, are multiplexed with the main
oscillator pins. They are enabled as oscillator or I/O
pins by the selection of the main oscillator in
Configuration Register 1H (see
for details). When they are not
used as port pins, RA6 and RA7 and their associated
TRIS and LAT bits are read as ‘0’.
The other PORTA pins are multiplexed with analog
inputs, the analog V
TRIS and LAT bits are read as ‘0’.
The other PORTA pins are multiplexed with analog
inputs, the analog V
REF
+ and V
REF
- inputs and the com-
parator voltage reference output. The operation of pins
RA<3:0> and RA5 as A/D Converter inputs is selected
by clearing/setting the control bits in the ANSEL0 and
ANSEL1 registers.
RA<3:0> and RA5 as A/D Converter inputs is selected
by clearing/setting the control bits in the ANSEL0 and
ANSEL1 registers.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 11-1:
INITIALIZING PORTA
Data
Bus
Bus
WR LAT
WR TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
Buffer
I/O Pin
(1)
Q
D
CK
Q
D
CK
EN
Q
D
EN
RD LAT
or PORT
Note 1:
I/O pins have diode protection to V
DD
and V
SS
.
Note 1:
On a Power-on Reset, RA<5:0> are
configured as analog inputs and read as ‘0’.
configured as analog inputs and read as ‘0’.
2:
RA5 I/F is available only on 40-pin
devices (PIC18F4331/4431).
devices (PIC18F4331/4431).
CLRF
PORTA
;
Initialize PORTA by
; clearing output
; data latches
CLRF
LATA
; Alternate method
; to clear output
; data latches
MOVLW
0x3F
; Configure A/D
MOVWF
ANSEL0
; for digital inputs
MOVLW
0xCF
; Value used to
; initialize data
; direction
MOVWF
TRISA
;
Set RA<3:0> as inputs
;
RA<5:4> as outputs