Microchip Technology DM183021 Data Sheet
PIC18F2331/2431/4331/4431
DS39616D-page 136
2010 Microchip Technology Inc.
14.0
TIMER2 MODULE
The Timer2 module has the following features:
• 8-bit Timer register (TMR2)
• 8-bit Period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2
• SSP module optional use of TMR2 output to
• 8-bit Timer register (TMR2)
• 8-bit Period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2
• SSP module optional use of TMR2 output to
generate clock shift
TMR2 can be shut off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
(T2CON<2>), to minimize power consumption.
is a simplified block diagram of the Timer2
module.
shows the Timer2 Control
register. The prescaler and postscaler selection of
Timer2 are controlled by this register.
Timer2 are controlled by this register.
14.1
Timer2 Operation
Timer2 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
Reset. The input clock (F
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
Reset. The input clock (F
OSC
/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits,
T2CKPS<1:0> (T2CON<1:0>). The match output of
TMR2 goes through a 4-bit postscaler (which gives a
1:1 to 1:16 scaling inclusive) to generate a TMR2
interrupt, latched in flag bit, TMR2IF (PIR1<1>).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (Power-on Reset, MCLR Reset,
T2CKPS<1:0> (T2CON<1:0>). The match output of
TMR2 goes through a 4-bit postscaler (which gives a
1:1 to 1:16 scaling inclusive) to generate a TMR2
interrupt, latched in flag bit, TMR2IF (PIR1<1>).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 14-1:
T2CON: TIMER2 CONTROL REGISTER
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented:
Read as ‘0’
bit 6-3
TOUTPS<3:0>:
Timer2 Output Postscale Select bits
0000
= 1:1 Postscale
0001
= 1:2 Postscale
•
•
•
1111
•
•
1111
= 1:16 Postscale
bit 2
TMR2ON:
Timer2 On bit
1
= Timer2 is on
0
= Timer2 is off
bit 1-0
T2CKPS<1:0>:
Timer2 Clock Prescale Select bits
00
= Prescaler is 1
01
= Prescaler is 4
1x
= Prescaler is 16