Microchip Technology DM183021 Data Sheet
PIC18F2331/2431/4331/4431
DS39616D-page 140
2010 Microchip Technology Inc.
FIGURE 15-1:
TIMER5 BLOCK DIAGRAM (16-BIT READ/WRITE MODE SHOWN)
15.1
Timer5 Operation
Timer5 combines two 8-bit registers to function as a
16-bit timer. The TMR5L register is the actual low byte
of the timer; it can be read and written to directly. The
high byte is contained in an unmapped register; it is
read and written to through TMR5H, which serves as
a buffer. Each register increments from 00h to FFh.
A second register pair, PR5H and PR5L, serves as the
Period register; it sets the maximum count for the
TMR5 register pair. When TMR5 reaches the value of
PR5, the timer rolls over to 00h and sets the TMR5IF
interrupt flag. A simplified block diagram of the Timer5
module is shown in Figure 2-1.
16-bit timer. The TMR5L register is the actual low byte
of the timer; it can be read and written to directly. The
high byte is contained in an unmapped register; it is
read and written to through TMR5H, which serves as
a buffer. Each register increments from 00h to FFh.
A second register pair, PR5H and PR5L, serves as the
Period register; it sets the maximum count for the
TMR5 register pair. When TMR5 reaches the value of
PR5, the timer rolls over to 00h and sets the TMR5IF
interrupt flag. A simplified block diagram of the Timer5
module is shown in Figure 2-1.
Timer5 supports three configurations:
• 16-Bit Synchronous Timer
• 16-Bit Synchronous Counter
• 16-Bit Asynchronous Counter
In Synchronous Timer configuration, the timer is
clocked by the internal device clock. The optional
Timer5 prescaler divides the input by 2, 4, 8 or not at all
(1:1). The TMR5 register pair increments on Q1.
Clearing TMR5CS (= 0) selects the internal device
clock as the timer sampling clock.
• 16-Bit Synchronous Timer
• 16-Bit Synchronous Counter
• 16-Bit Asynchronous Counter
In Synchronous Timer configuration, the timer is
clocked by the internal device clock. The optional
Timer5 prescaler divides the input by 2, 4, 8 or not at all
(1:1). The TMR5 register pair increments on Q1.
Clearing TMR5CS (= 0) selects the internal device
clock as the timer sampling clock.
T5SYNC
TMR5CS
T5PS<1:0>
T5PS<1:0>
Sleep Input
F
OSC
/4
Internal
Clock
1
0
2
T5CKI
1
0
TMR5L
Internal Data Bus
TMR5
TMR5H
High Byte
8
8
Write TMR5L
Read TMR5L
8
TMR5ON
On/Off
Timer5
PR5L
16
PR5H
8
8
Comparator
16
8
1
0
TMR5
PR5
Reset
Logic
Special
Event
Logic
Timer5 Reset
Set TMR5IF
Timer5 Reset
(external)
(external)
Special Event
Trigger Output
Trigger Output
Special Event
Trigger Input
from IC1
Trigger Input
from IC1
Noise
Filter
Prescaler
1, 2, 4, 8
Synchronize
Detect
Note:
The Timer5 may be used as a general pur-
pose timer and as the time base resource to
the Motion Feedback Module (Input
Capture or Quadrature Encoder Interface).
pose timer and as the time base resource to
the Motion Feedback Module (Input
Capture or Quadrature Encoder Interface).