Microchip Technology DM183021 Data Sheet
PIC18F2331/2431/4331/4431
DS39616D-page 156
2010 Microchip Technology Inc.
When in Counter mode, the counter must be
configured as the synchronous counter only
(T5SYNC = 0). When configured in Asynchronous
mode, the IC module will not work properly.
configured as the synchronous counter only
(T5SYNC = 0). When configured in Asynchronous
mode, the IC module will not work properly.
17.1.1
EDGE CAPTURE MODE
In this mode, the value of the time base is captured
either on every rising edge, every falling edge, every
4th rising edge, or every 16th rising edge. The edge
present on the input capture pin (CAP1, CAP2 or
CAP3) is sampled by the synchronizing latch. The
signal is used to load the Input Capture Buffer (ICxBUF
register) on the following Q1 clock (see
either on every rising edge, every falling edge, every
4th rising edge, or every 16th rising edge. The edge
present on the input capture pin (CAP1, CAP2 or
CAP3) is sampled by the synchronizing latch. The
signal is used to load the Input Capture Buffer (ICxBUF
register) on the following Q1 clock (see
Consequently, Timer5 is either reset to ‘0’ (Q1
immediately following the capture event) or left free
running, depending on the setting of the Capture Reset
Enable bit, CAPxREN, in the CAPxCON register.
immediately following the capture event) or left free
running, depending on the setting of the Capture Reset
Enable bit, CAPxREN, in the CAPxCON register.
FIGURE 17-4:
EDGE CAPTURE MODE TIMING
Note 1:
Input capture prescalers are reset
(cleared) when the input capture module
is disabled (CAPxM = 0000).
(cleared) when the input capture module
is disabled (CAPxM = 0000).
2:
When the Input Capture mode is
changed, without first disabling the
module and entering the new Input Cap-
ture mode, a false interrupt (or Special
Event Trigger on IC1) may be generated.
The user should either: (1) disable the
input capture before entering another
mode, or (2) disable IC interrupts to avoid
false interrupts during IC mode changes.
changed, without first disabling the
module and entering the new Input Cap-
ture mode, a false interrupt (or Special
Event Trigger on IC1) may be generated.
The user should either: (1) disable the
input capture before entering another
mode, or (2) disable IC interrupts to avoid
false interrupts during IC mode changes.
3:
During IC mode changes, the prescaler
count will not be cleared, therefore, the
first capture in the new IC mode may be
from the non-zero prescaler.
count will not be cleared, therefore, the
first capture in the new IC mode may be
from the non-zero prescaler.
Note:
On the first capture edge following the
setting of the Input Capture mode (i.e.,
MOVWF CAP1CON
setting of the Input Capture mode (i.e.,
MOVWF CAP1CON
), Timer5 contents are
always captured into the corresponding
Input Capture Buffer (i.e., CAPxBUF).
Timer5 can optionally be reset; however,
this is dependent on the setting of the
Capture Reset Enable bit, CAPxREN (see
Input Capture Buffer (i.e., CAPxBUF).
Timer5 can optionally be reset; however,
this is dependent on the setting of the
Capture Reset Enable bit, CAPxREN (see
).
CAP1 Pin
(2)
0000
0002
0000
0001
0002
TMR5
(1)
CAP1BUF
(3)
0002
0014
0013
0012
0015
ABCD
0001
0003
TMR5 Reset
(4)
MOVWF CAP1CON
BCF CAP1CON, CAP1REN
Note 5
0016
Instruction
Note 1:
TMR5 is a synchronous time base input to the input capture; prescaler = 1:1. It increments on the Q1 rising edge.
2:
IC1 is configured in Edge Capture mode (CAP1M<3:0> = 0010) with the time base reset upon edge capture
(CAP1REN = 1) and no noise filter.
(CAP1REN = 1) and no noise filter.
3:
TMR5 value is latched by CAP1BUF on T
CY
. In the event that a write to TMR5 coincides with an input capture event,
the write will always take precedence. All Input Capture Buffers, CAP1BUF, CAP2BUF and CAP3BUF, are updated
with the incremented value of the time base on the next T
with the incremented value of the time base on the next T
CY
clock edge when the capture event takes place (see
Note 4
when Reset occurs).
4:
TMR5 Reset is normally an asynchronous Reset signal to TMR5. When used with the input capture, it is active
immediately after the time base value is captured.
immediately after the time base value is captured.
5:
TMR5 Reset pulse is disabled by clearing the CAP1REN bit (e.g., BCF CAP1CON, CAP1REN).
OSC
Execution
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4