Microchip Technology DM183021 Data Sheet
2010 Microchip Technology Inc.
DS39616D-page 187
PIC18F2331/2431/4331/4431
18.6
PWM Duty Cycle
PWM duty cycle is defined by the PDCx (PDCxL and
PDCxH) registers. There are a total of four PWM Duty
Cycle registers for four pairs of PWM channels. The
Duty Cycle registers have 14-bit resolution by combin-
ing six LSbs of PDCxH with the 8 bits of PDCxL. PDCx
is a double-buffered register used to set the counting
period for the PWM time base.
PDCxH) registers. There are a total of four PWM Duty
Cycle registers for four pairs of PWM channels. The
Duty Cycle registers have 14-bit resolution by combin-
ing six LSbs of PDCxH with the 8 bits of PDCxL. PDCx
is a double-buffered register used to set the counting
period for the PWM time base.
18.6.1
PWM DUTY CYCLE REGISTERS
There are four 14-bit Special Function Registers used
to specify duty cycle values for the PWM module:
• PDC0 (PDC0L and PDC0H)
• PDC1 (PDC1L and PDC1H)
• PDC2 (PDC2L and PDC2H)
• PDC3 (PDC3L and PDC3H)
to specify duty cycle values for the PWM module:
• PDC0 (PDC0L and PDC0H)
• PDC1 (PDC1L and PDC1H)
• PDC2 (PDC2L and PDC2H)
• PDC3 (PDC3L and PDC3H)
The value in each Duty Cycle register determines the
amount of time that the PWM output is in the active
state. The upper 12 bits of PDCx holds the actual duty
cycle value from PTMRH/L<11:0>, while the lower
2 bits control which internal Q clock the duty cycle
match will occur. This 2-bit value is decoded from the Q
clocks as shown in
amount of time that the PWM output is in the active
state. The upper 12 bits of PDCx holds the actual duty
cycle value from PTMRH/L<11:0>, while the lower
2 bits control which internal Q clock the duty cycle
match will occur. This 2-bit value is decoded from the Q
clocks as shown in
(when the prescaler is
1:1 or PTCKPS<1:0> = 00).
In Edge-Aligned mode, the PWM period starts at Q1
and ends when the Duty Cycle register matches the
PTMR register as follows. The duty cycle match is con-
sidered when the upper 12 bits of the PDCx are equal
to the PTMR and the lower 2 bits are equal to Q1, Q2,
Q3 or Q4, depending on the lower two bits of the PDCx
(when the prescaler is 1:1 or PTCKPS<1:0> = 00)
In Edge-Aligned mode, the PWM period starts at Q1
and ends when the Duty Cycle register matches the
PTMR register as follows. The duty cycle match is con-
sidered when the upper 12 bits of the PDCx are equal
to the PTMR and the lower 2 bits are equal to Q1, Q2,
Q3 or Q4, depending on the lower two bits of the PDCx
(when the prescaler is 1:1 or PTCKPS<1:0> = 00)
.
Each compare unit has logic that allows override of the
PWM signals. This logic also ensures that the PWM
signals will complement each other (with dead-time
insertion) in Complementary mode (see
PWM signals. This logic also ensures that the PWM
signals will complement each other (with dead-time
insertion) in Complementary mode (see
).
FIGURE 18-11:
DUTY CYCLE COMPARISON
Note:
When the prescaler is not 1:1
(PTCKPS<1:0>
(PTCKPS<1:0>
~00), the duty cycle
match occurs at the Q1 clock of the
instruction cycle when the PTMR and
PDCx match occurs.
instruction cycle when the PTMR and
PDCx match occurs.
PTMR<11:0>
PDCx<13:0>
Comparator
Unused
Unused
PTMRH<7:0>
PTMRL<7:0>
PTMRH<3:0>
PTMRL<7:0>
Q Clocks
(1)
PDCxH<7:0>
PDCxL<7:0>
PDCxH<5:0>
PDCxL<7:0>
<1:0>
Note 1:
This value is decoded from the Q clocks:
00
= duty cycle match occurs on Q1
01
= duty cycle match occurs on Q2
10
= duty cycle match occurs on Q3
11
= duty cycle match occurs on Q4