Microchip Technology DM183021 Data Sheet
PIC18F2331/2431/4331/4431
DS39616D-page 202
2010 Microchip Technology Inc.
18.13 PWM Update Lockout
For a complex PWM application, the user may need to
write up to four Duty Cycle registers and the PWM Time
Base Period register, PTPER, at a given time. In some
applications, it is important that all buffer registers be
written before the new duty cycle and period values are
loaded for use by the module.
A PWM update lockout feature may optionally be
enabled so the user may specify when new duty cycle
buffer values are valid. The PWM update lockout
feature is enabled by setting the control bit, UDIS, in
the PWMCON1 register. This bit affects all Duty Cycle
Buffer registers and the PWM Time Base Period
register, PTPER.
To perform a PWM update lockout:
1.
write up to four Duty Cycle registers and the PWM Time
Base Period register, PTPER, at a given time. In some
applications, it is important that all buffer registers be
written before the new duty cycle and period values are
loaded for use by the module.
A PWM update lockout feature may optionally be
enabled so the user may specify when new duty cycle
buffer values are valid. The PWM update lockout
feature is enabled by setting the control bit, UDIS, in
the PWMCON1 register. This bit affects all Duty Cycle
Buffer registers and the PWM Time Base Period
register, PTPER.
To perform a PWM update lockout:
1.
Set the UDIS bit.
2.
Write all Duty Cycle registers and PTPER, if
applicable.
applicable.
3.
Clear the UDIS bit to re-enable updates.
4.
With this, when UDIS bit is cleared, the buffer
values will be loaded to the actual registers. This
makes a synchronous loading of the registers.
values will be loaded to the actual registers. This
makes a synchronous loading of the registers.
18.14 PWM Special Event Trigger
The PWM module has a Special Event Trigger capabil-
ity that allows A/D conversions to be synchronized to
the PWM time base. The A/D sampling and conversion
time may be programmed to occur at any point within
the PWM period. The Special Event Trigger allows the
user to minimize the delay between the time when A/D
conversion results are acquired and the time when the
duty cycle value is updated.
The PWM 16-bit Special Event Trigger register,
SEVTCMP (high and low), and five control bits in the
PWMCON1 register are used to control its operation.
ity that allows A/D conversions to be synchronized to
the PWM time base. The A/D sampling and conversion
time may be programmed to occur at any point within
the PWM period. The Special Event Trigger allows the
user to minimize the delay between the time when A/D
conversion results are acquired and the time when the
duty cycle value is updated.
The PWM 16-bit Special Event Trigger register,
SEVTCMP (high and low), and five control bits in the
PWMCON1 register are used to control its operation.
The PTMR value for which a Special Event Trigger
should occur is loaded into the SEVTCMP register pair.
The SEVTDIR bit in the PWMCON1 register specifies
the counting phase when the PWM time base is in a
Continuous Up/Down Count mode.
If the SEVTDIR bit is cleared, the Special Event Trigger
will occur on the upward counting cycle of the PWM
time base. If SEVTDIR is set, the Special Event Trigger
will occur on the downward count cycle of the PWM
time base. The SEVTDIR bit has effect only when the
PWM timer is in the Continuous Up/Down Count mode.
should occur is loaded into the SEVTCMP register pair.
The SEVTDIR bit in the PWMCON1 register specifies
the counting phase when the PWM time base is in a
Continuous Up/Down Count mode.
If the SEVTDIR bit is cleared, the Special Event Trigger
will occur on the upward counting cycle of the PWM
time base. If SEVTDIR is set, the Special Event Trigger
will occur on the downward count cycle of the PWM
time base. The SEVTDIR bit has effect only when the
PWM timer is in the Continuous Up/Down Count mode.
18.14.1
SPECIAL EVENT TRIGGER ENABLE
The PWM module will always produce Special Event
Trigger pulses. This signal may optionally be used by
the A/D module. Refer to
Trigger pulses. This signal may optionally be used by
the A/D module. Refer to
for details.
18.14.2
SPECIAL EVENT TRIGGER
POSTSCALER
POSTSCALER
The PWM Special Event Trigger has a postscaler that
allows a 1:1 to 1:16 postscale ratio. The postscaler is
configured by writing the SEVOPS<3:0> control bits in
the PWMCON1 register.
The Special Event Trigger output postscaler is cleared
on any write to the SEVTCMP register pair, or on any
device Reset.
allows a 1:1 to 1:16 postscale ratio. The postscaler is
configured by writing the SEVOPS<3:0> control bits in
the PWMCON1 register.
The Special Event Trigger output postscaler is cleared
on any write to the SEVTCMP register pair, or on any
device Reset.