Microchip Technology DM183021 Data Sheet
PIC18F2331/2431/4331/4431
DS39616D-page 30
2010 Microchip Technology Inc.
TABLE 3-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
CRYSTAL OSCILLATOR
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in
OSC1 pin in the HS mode, as shown in
FIGURE 3-2:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
OPERATION (HS OSC
CONFIGURATION)
3.3
PLL Frequency Multiplier
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for those concerned with EMI from high-
frequency crystals or users requiring higher clock
speeds from an internal oscillator.
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for those concerned with EMI from high-
frequency crystals or users requiring higher clock
speeds from an internal oscillator.
3.3.1
HSPLL OSCILLATOR MODE
The HSPLL mode uses the HS Oscillator mode for
frequencies up to 10 MHz. A PLL circuit then multiplies
the oscillator output frequency by four to produce an
internal clock frequency up to 40 MHz. The PLLEN bit
is not available in this oscillator mode.
The PLL is only available to the crystal oscillator when
the FOSC<3:0> Configuration bits are programmed for
HSPLL mode (‘0110’).
frequencies up to 10 MHz. A PLL circuit then multiplies
the oscillator output frequency by four to produce an
internal clock frequency up to 40 MHz. The PLLEN bit
is not available in this oscillator mode.
The PLL is only available to the crystal oscillator when
the FOSC<3:0> Configuration bits are programmed for
HSPLL mode (‘0110’).
FIGURE 3-3:
PLL BLOCK DIAGRAM
Osc Type
Crystal
Freq
Typical Capacitor Values
Tested:
C1
C2
LP
32 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
XT
1 MHz
33 pF
33 pF
4 MHz
27 pF
27 pF
HS
4 MHz
27 pF
27 pF
8 MHz
22 pF
22 pF
20 MHz
15 pF
15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
below for basic start-up and operation. These values
are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
V
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
V
DD
and temperature range for the application.
See the notes following this table for additional
information.
information.
Crystals Used:
32 kHz
4 MHz
200 kHz
8 MHz
1 MHz
20 MHz
Note 1:
Higher capacitance increases the
stability of oscillator, but also increases
the start-up time.
stability of oscillator, but also increases
the start-up time.
2:
When operating below 3V V
DD
, or when
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
3:
Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4:
Rs may be required to avoid overdriving
crystals with low drive level specification.
crystals with low drive level specification.
5:
Always verify oscillator performance over
the V
the V
DD
and temperature range that is
expected for the application.
OSC1
OSC2
Open
Clock from
Ext. System
Ext. System
PIC18FXXXX
(HS Mode)
MU
X
VCO
Loop
Filter
Crystal
Osc
OSC2
OSC1
PLL Enable
F
IN
F
OUT
SYSCLK
Phase
Comparator
HS Osc Enable
4
(from Configuration Register 1H)
HS Mode