Microchip Technology DM183021 Data Sheet
PIC18F2331/2431/4331/4431
DS39616D-page 46
2010 Microchip Technology Inc.
4.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped; and
• the primary clock source is not any of the LP, XT,
HS or HSPLL modes.
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval,
T
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval,
T
CSD
, following the wake event, is still required when
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
TABLE 4-2:
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
(BY CLOCK SOURCES)
Clock Source
Before Wake-up
Clock Source
After Wake-up
Exit Delay
Clock Ready Status
Bit (OSCCON)
Primary Device Clock
(PRI_IDLE mode)
LP, XT, HS
T
CSD(1)
OSTS
HSPLL
EC, RC
INTOSC
(2)
IOFS
T1OSC
LP, XT, HS
T
OST(3)
OSTS
HSPLL
T
OST
+ t
rc
(3)
EC, RC
T
CSD(1)
INTOSC
(2)
T
IOBST(4)
IOFS
INTOSC
(3)
LP, XT, HS
T
OST(3)
OSTS
HSPLL
T
OST
+ t
rc
(3)
EC, RC
T
CSD(1)
INTOSC
(2)
None
IOFS
None
(Sleep mode)
LP, XT, HS
T
OST(3)
OSTS
HSPLL
T
OST
+ t
rc
(3)
EC, RC
T
CSD(1)
INTOSC
(2)
T
IOBST(4)
IOFS
Note 1:
T
CSD
(Parameter 38) is a required delay when waking from Sleep and all Idle modes, and runs concur-
2:
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
3:
T
OST
is the Oscillator Start-up Timer (Parameter 32). t
rc
is the PLL Lock-out Timer (Parameter F12); it is
also designated as T
PLL
.
4:
Execution continues during T
IOBST
(Parameter 39), the INTOSC stabilization period.