Microchip Technology ARD00385 Data Sheet
2009-2011 Microchip Technology Inc.
DS39957D-page 119
PIC18F87K90 FAMILY
EXAMPLE 7-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
7.5.2
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
7.5.4
PROTECTION AGAINST
SPURIOUS WRITES
SPURIOUS WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See
memory, the write initiate sequence must also be
followed. See
for more details.
7.6
Flash Program Operation During
Code Protection
Code Protection
See
program memory.
TABLE 7-2:
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
PROGRAM_MEMORY
BSF
EECON1, EEPGD
; point to Flash program memory
BCF
EECON1, CFGS
; access Flash program memory
BSF
EECON1, WREN
; enable write to memory
BCF
INTCON, GIE
; disable interrupts
MOVLW
0x55
Required
MOVWF
EECON2
; write 55h
Sequence
MOVLW
0xAA
MOVWF
EECON2
; write 0AAh
BSF
EECON1, WR
; start program (CPU stall)
BSF
INTCON, GIE
; re-enable interrupts
BCF
EECON1, WREN
; disable write to memory
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
Page:
TBLPTRU
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
Program Memory Table Latch
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
EECON2
EEPROM Control Register 2 (not a physical register)
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
IPR6
—
—
—
EEIP
—
CMP3IP
CMP2IP
CMP1IP
PIR6
—
—
—
EEIF
—
CMP3IF
CMP2IF
CMP1IF
PIE6
—
—
—
EEIE
—
CMP3IE
CMP2IE
CMP1IE
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1:
Bit 21 of TBLPTRU allows access to the device Configuration bits.