Microchip Technology ARD00385 Data Sheet
PIC18F87K90 FAMILY
DS39957D-page 134
2009-2011 Microchip Technology Inc.
10.2
PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are six Peripheral Interrupt
Request (Flag) registers (PIR1 through PIR6).
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are six Peripheral Interrupt
Request (Flag) registers (PIR1 through PIR6).
Note 1:
Interrupt flag bits are set when an
interrupt condition occurs, regardless of
the state of its corresponding enable bit or
the Global Interrupt Enable bit, GIE
(INTCON<7>).
interrupt condition occurs, regardless of
the state of its corresponding enable bit or
the Global Interrupt Enable bit, GIE
(INTCON<7>).
2:
User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
REGISTER 10-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
U-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
—
ADIF
RC1IF
TX1IF
SSP1IF
TMR1GIF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented:
Read as ‘0’
bit 6
ADIF:
A/D Converter Interrupt Flag bit
1
= An A/D conversion completed (must be cleared in software)
0
= The A/D conversion is not complete
bit 5
RC1IF:
EUSART Receive Interrupt Flag bit
1
= The EUSART receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0
= The EUSART receive buffer is empty
bit 4
TX1IF:
EUSART Transmit Interrupt Flag bit
1
= The EUSART transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0
= The EUSART transmit buffer is full
bit 3
SSP1IF:
Master Synchronous Serial Port Interrupt Flag bit
1
= The transmission/reception is complete (must be cleared in software)
0
= Waiting to transmit/receive
bit 2
TMR1GIF:
Timer1 Gate Interrupt Flag bit
1
= Timer gate interrupt has occurred (must be cleared in software)
0
= No timer gate interrupt has occurred
bit 1
TMR2IF:
TMR2 to PR2 Match Interrupt Flag bit
1
= TMR2 to PR2 match has occurred (must be cleared in software)
0
= No TMR2 to PR2 match has occurred
bit 0
TMR1IF:
TMR1 Overflow Interrupt Flag bit
1
= TMR1 register overflowed (must be cleared in software)
0
= TMR1 register did not overflow