Microchip Technology ARD00385 Data Sheet
PIC18F87K90 FAMILY
DS39957D-page 142
2009-2011 Microchip Technology Inc.
REGISTER 10-12: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TMR5GIE
LCDIE
(
)
RC2IE
TX2IE
CTMUIE
CCP2IE
CCP1IE
RTCCIE
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR5GIE:
Timer5 Gate Interrupt Enable bit
1
= Enabled
0
= Disabled
bit 6
LCDIE:
LCD Interrupt Enable bit
)
1
= Enabled
0
= Disabled
bit 5
RC2IE:
AUSART Receive Interrupt Enable bit
1
= Enabled
0
= Disabled
bit 4
TX2IE:
AUSART Transmit Interrupt Enable bit
1
= Enabled
0
= Disabled
bit 3
CTMUIE:
CTMU Interrupt Enable bit
1
= Enabled
0
= Disabled
bit 2
CCP2IE:
ECCP2 Interrupt Enable bit
1
= Enabled
0
= Disabled
bit 1
CCP1IE:
ECCP1 Interrupt Enable bit
1
= Enabled
0
= Disabled
bit 0
RTCCIE:
RTCC Interrupt Enable bit
1
= Enabled
0
= Disabled
Note 1:
This bit is valid when the Type-B waveform with Non-Static mode is selected.
REGISTER 10-13: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCP10IE
(
)
CCP9IE
CCP8IE
CCP7IE
CCP6IE
CCP5IE
CCP4IE
CCP3IE
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
CCP10IE:CCP3IE:
CCP<10:3> Interrupt Enable bits
1
= Enabled
0
= Disabled
Note 1:
CCP10IE and CCP9IE are unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90).