Microchip Technology ARD00385 Data Sheet
PIC18F87K90 FAMILY
DS39957D-page 170
2009-2011 Microchip Technology Inc.
TABLE 11-10: PORTE FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RE0/LCDBIAS1/
P2D
P2D
RE0
0
O
DIG
LATE<0> data output.
1
I
ST
PORTE<0> data input.
LCDBIAS1
—
I
ANA
LCD module bias voltage input.
P2D
0
O
—
ECCP2 PWM Output D. May be configured for tri-state during
Enhanced PWM shutdown events.
Enhanced PWM shutdown events.
RE1/LCDBIAS2/
P2C
P2C
RE1
0
O
DIG
LATE<1> data output.
1
I
ST
PORTE<1> data input.
LCDBIAS2
—
I
ANA
LCD module bias voltage input.
P2C
0
O
—
ECCP2 PWM Output C.
May be configured for tri-state during Enhanced PWM shutdown events.
May be configured for tri-state during Enhanced PWM shutdown events.
RE2/LCDBIAS3/
P2B
P2B
RE2
0
O
DIG
LATE<2> data output.
1
I
ST
PORTE<2> data input.
LCDBIAS3
x
I
ANA
LCD module bias voltage input.
P2B
0
O
—
ECCP2 PWM Output B. May be configured for tri-state during
Enhanced PWM shutdown events.
Enhanced PWM shutdown events.
RE3/COM0/
P3C/CCP9/
REFO
P3C/CCP9/
REFO
RE3
0
O
DIG
LATE<3> data output.
1
I
ST
PORTE<3> data input.
COM0
x
O
ANA
LCD Common 0 output; disables all other outputs.
P3C
0
O
—
ECCP3 PWM Output C. May be configured for tri-state during
Enhanced PWM shutdown events.
Enhanced PWM shutdown events.
CCP9
(
0
O
DIG
CCP9 compare/PWM output; takes priority over port data.
1
I
ST
CCP9 capture input.
REFO
x
O
DIG
Reference output clock.
RE4/COM1/
P3B/CCP8
P3B/CCP8
RE4
0
O
DIG
LATE<4> data output.
1
I
ST
PORTE<4> data input.
COM1
x
O
ANA
LCD Common 1 output; disables all other outputs.
P3B
0
O
—
ECCP3 PWM Output B. May be configured for tri-state during
Enhanced PWM shutdown events.
Enhanced PWM shutdown events.
CCP8
0
O
DIG
CCP8 Compare/PWM output; takes priority over port data.
1
I
ST
CCP8 capture input.
RE5/COM2/
P1C/CCP7
P1C/CCP7
RE5
0
O
DIG
LATE<5> data output.
1
I
ST
PORTE<5> data input.
COM2
x
O
ANA
LCD Common 2 output; disables all other outputs.
P1C
0
O
—
ECCP1 PWM Output C. May be configured for tri-state during
Enhanced PWM shutdown events.
Enhanced PWM shutdown events.
CCP7
0
O
DIG
CCP7 Compare/PWM output; takes priority over port data.
1
I
ST
CCP7 capture input.
RE6/COM3/
P1B/CCP6
P1B/CCP6
RE6
0
O
DIG
LATE<6> data output.
1
I
ST
PORTE<6> data input.
COM3
x
O
ANA
LCD Common 3 output; disables all other outputs.
P1B
0
O
—
ECCP1 PWM Output B. May be configured for tri-state during
Enhanced PWM shutdown events.
Enhanced PWM shutdown events.
CCP6
0
O
DIG
CCP6 Compare/PWM output; takes priority over port data.
1
I
ST
CCP6 capture input.
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x
x
= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note
1:
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
2:
This bit is unimplemented in PIC18FX5K90 devices.