Microchip Technology ARD00385 Data Sheet
PIC18F87K90 FAMILY
DS39957D-page 206
2009-2011 Microchip Technology Inc.
15.3
Timer3/5/7 16-Bit Read/Write Mode
). When the RD16 control bit
(TxCON<1>) is set, the address for TMRxH is mapped
to a buffer register for the high byte of Timer3/5/7. A
read from TMRxL will load the contents of the high byte
of Timer3/5/7 into the Timerx High Byte Buffer register.
This provides users with the ability to accurately read
all 16 bits of Timer3/5/7 without having to determine
whether a read of the high byte, followed by a read of
the low byte, has become invalid due to a rollover
between reads.
A write to the high byte of Timer3/5/7 must also take
place through the TMRxH Buffer register. The Timer3/
5/7 high byte is updated with the contents of TMRxH
when a write occurs to TMRxL. This allows users to
write all 16 bits to both the high and low bytes of
Timer3/5/7 at once.
The high byte of Timer3/5/7 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timerx High Byte Buffer register.
Writes to TMRxH do not clear the Timer3/5/7 prescaler.
The prescaler is only cleared on writes to TMRxL.
to a buffer register for the high byte of Timer3/5/7. A
read from TMRxL will load the contents of the high byte
of Timer3/5/7 into the Timerx High Byte Buffer register.
This provides users with the ability to accurately read
all 16 bits of Timer3/5/7 without having to determine
whether a read of the high byte, followed by a read of
the low byte, has become invalid due to a rollover
between reads.
A write to the high byte of Timer3/5/7 must also take
place through the TMRxH Buffer register. The Timer3/
5/7 high byte is updated with the contents of TMRxH
when a write occurs to TMRxL. This allows users to
write all 16 bits to both the high and low bytes of
Timer3/5/7 at once.
The high byte of Timer3/5/7 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timerx High Byte Buffer register.
Writes to TMRxH do not clear the Timer3/5/7 prescaler.
The prescaler is only cleared on writes to TMRxL.
15.4
Using the SOSC Oscillator as the
Timer3/5/7 Clock Source
Timer3/5/7 Clock Source
The SOSC internal oscillator may be used as the clock
source for Timer3/5/7. The SOSC oscillator is enabled by
setting one of five bits: any of the four SOSCEN bits in the
TxCON registers (TxCON<3>) or the SOSCGO bit in the
OSCCON2 register (OSCCON2<3>). To use it as the
Timer3/5/7 clock source, the TMRxCS bit must also be
set. As previously noted, this also configures Timer3/5/7
to increment on every rising edge of the oscillator source.
The SOSC oscillator is described in
source for Timer3/5/7. The SOSC oscillator is enabled by
setting one of five bits: any of the four SOSCEN bits in the
TxCON registers (TxCON<3>) or the SOSCGO bit in the
OSCCON2 register (OSCCON2<3>). To use it as the
Timer3/5/7 clock source, the TMRxCS bit must also be
set. As previously noted, this also configures Timer3/5/7
to increment on every rising edge of the oscillator source.
The SOSC oscillator is described in
15.5
Timer3/5/7 Gates
Timer3/5/7 can be configured to count freely or the
count can be enabled and disabled using the Timer3/
5/7 gate circuitry. This is also referred to as the
Timer3/5/7 gate count enable.
The Timer3/5/7 gate can also be driven by multiple
selectable sources.
count can be enabled and disabled using the Timer3/
5/7 gate circuitry. This is also referred to as the
Timer3/5/7 gate count enable.
The Timer3/5/7 gate can also be driven by multiple
selectable sources.
15.5.1
TIMER3/5/7 GATE COUNT ENABLE
The Timerx Gate Enable mode is enabled by setting
the TMRxGE bit (TxGCON<7>). The polarity of the
Timerx Gate Enable mode is configured using the
TxGPOL bit (TxGCON<6>).
When Timerx Gate Enable mode is enabled, Timer3/5/7
will increment on the rising edge of the Timer3/5/7 clock
source. When Timerx Gate Enable mode is disabled, no
incrementing will occur and Timer3/5/7 will hold the
current count. See
the TMRxGE bit (TxGCON<7>). The polarity of the
Timerx Gate Enable mode is configured using the
TxGPOL bit (TxGCON<6>).
When Timerx Gate Enable mode is enabled, Timer3/5/7
will increment on the rising edge of the Timer3/5/7 clock
source. When Timerx Gate Enable mode is disabled, no
incrementing will occur and Timer3/5/7 will hold the
current count. See
for timing details.
TABLE 15-1:
TIMER3/5/7 GATE ENABLE
SELECTIONS
SELECTIONS
FIGURE 15-2:
TIMER3/5/7 GATE COUNT ENABLE MODE
TxCLK
(
)
TxGPOL
(TxGCON<6>)
TxG Pin
Timerx Operation
0
0
Counts
0
1
Holds Count
1
0
Holds Count
1
1
Counts
† The clock on which TMR3/5/7 is running. For more
information, see TxCLK in
TMRxGE
TxGPOL
TxG_IN
TxCKI
TxGVAL
Timer3/5/7
N
N + 1
N + 2
N + 3
N + 4