Microchip Technology ARD00385 Data Sheet
PIC18F87K90 FAMILY
DS39957D-page 242
2009-2011 Microchip Technology Inc.
18.1.2
OPEN-DRAIN OUTPUT OPTION
When operating in Output mode (the Compare or PWM
modes), the drivers for the CCPx pins can be optionally
configured as open-drain outputs. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor and allows the
output to communicate with external circuits without the
need for additional level shifters.
The open-drain output option is controlled by the
CCPxOD bits (ODCON2<7:2>). Setting the appropriate
bit configures the pin for the corresponding module for
open-drain operation.
modes), the drivers for the CCPx pins can be optionally
configured as open-drain outputs. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor and allows the
output to communicate with external circuits without the
need for additional level shifters.
The open-drain output option is controlled by the
CCPxOD bits (ODCON2<7:2>). Setting the appropriate
bit configures the pin for the corresponding module for
open-drain operation.
18.1.3
PIN ASSIGNMENT FOR CCP6,
CCP7, CCP8 AND CCP9
CCP7, CCP8 AND CCP9
The pin assignment for CCP6/7/8/9 (Capture input,
Compare and PWM output) can change, based on the
device configuration.
The ECCPMX Configuration bit (CONFIG3H<1>)
determines the pin to which CCP6/7/8/9 is multiplexed.
The pin assignments for these CCP modules are given
in
Compare and PWM output) can change, based on the
device configuration.
The ECCPMX Configuration bit (CONFIG3H<1>)
determines the pin to which CCP6/7/8/9 is multiplexed.
The pin assignments for these CCP modules are given
in
.
TABLE 18-4:
CCP PIN ASSIGNMENT
18.2
Capture Mode
In Capture mode, the CCPR4H:CCPR4L register pair
captures the 16-bit value of the TMR1 or TMR3 register
when an event occurs on the CCP4 pins. An event is
defined as one of the following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The event is selected by the mode select bits,
CCP4M<3:0> (CCP4CON<3:0>). When a capture is
made, the interrupt request flag bit, CCP4IF (PIR4<1>),
is set. (It must be cleared in software.) If another
capture occurs before the value in CCPR4 is read, the
old captured value is overwritten by the new captured
value.
captures the 16-bit value of the TMR1 or TMR3 register
when an event occurs on the CCP4 pins. An event is
defined as one of the following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The event is selected by the mode select bits,
CCP4M<3:0> (CCP4CON<3:0>). When a capture is
made, the interrupt request flag bit, CCP4IF (PIR4<1>),
is set. (It must be cleared in software.) If another
capture occurs before the value in CCPR4 is read, the
old captured value is overwritten by the new captured
value.
18.2.1
CCP PIN CONFIGURATION
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
configured as an input by setting the corresponding
TRIS direction bit.
18.2.2
TIMER1/3/5/7 MODE SELECTION
For the available timers (1/3/5/7) to be used for the cap-
ture feature, the used timers must be running in Timer
mode or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work.
The timer to be used with each CCP module is selected
in the CCPTMRSx registers. (See
ture feature, the used timers must be running in Timer
mode or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work.
The timer to be used with each CCP module is selected
in the CCPTMRSx registers. (See
Details of the timer assignments for the CCP modules
are given in
are given in
and
ECCPMX
Value
Pin Mapped To
CCP6
CCP7
CCP8
CC9
1
(Default)
RE6
RE5
RE4
RE3
0
RH7
RH6
RH5
RH4
Note:
If RC1 or RE7 is configured as a CCP4
output, a write to the PORT causes a
capture condition.
output, a write to the PORT causes a
capture condition.