Microchip Technology ARD00385 Data Sheet
2009-2011 Microchip Technology Inc.
DS39957D-page 363
PIC18F87K90 FAMILY
FIGURE 22-7:
ASYNCHRONOUS RECEPTION
TABLE 22-6:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
—
ADIF
RC1IF
TX1IF
SSP1IF
TMR1GIF TMR2IF
TMR1IF
PIE1
—
ADIE
RC1IE
TX1IE
SSP1IE
TMR1GIE
TMR2IE
TMR1IE
IPR1
—
ADIP
RC1IP
TX1IP
SSP1IP
TMR1GIP
TMR2IP
TMR1IP
PIR3
TMR5GIF
LCDIF
RC2IF
TX2IF
CTMUIF
CCP2IF
CCP1IF
RTCCIF
PIE3
TMR5GIE
LCDIE
RC2IE
TX2IE
CTMUIE
CCP2IE
CCP1IE
RTCCIE
IPR3
TMR5GIP
LCDIP
RC2IP
TX2IP
CTMUIP
CCP2IP
CCP1IP
RTCCIP
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RCREG1
EUSART1 Receive Register
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
BAUDCON1 ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
SPBRGH1
EUSART1 Baud Rate Generator Register High Byte
SPBRG1
EUSART1 Baud Rate Generator Register Low Byte
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RCREG2
EUSART2 Receive Register
TXSTA2
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
BAUDCON2 ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
SPBRGH2
EUSART2 Baud Rate Generator Register High Byte
SPBRG2
EUSART2 Baud Rate Generator Register Low Byte
Legend:
— = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Start
bit
bit 7/8
bit 1
bit 0
bit 7/8
bit 0
Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RXx (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREGx
Word 2
RCREGx
Stop
bit
Note:
This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
causing the OERR (Overrun) bit to be set.