Microchip Technology ARD00385 Data Sheet
2009-2011 Microchip Technology Inc.
DS39957D-page 425
PIC18F87K90 FAMILY
28.0
SPECIAL FEATURES OF THE
CPU
CPU
The PIC18F87K90 family of devices includes several
features intended to maximize reliability and minimize
cost through elimination of external components.
These include:
• Oscillator Selection
• Resets:
features intended to maximize reliability and minimize
cost through elimination of external components.
These include:
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT) and On-Chip Regulator
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• ID Locations
• In-Circuit Serial Programming™ (ICSP™)
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in
• Watchdog Timer (WDT) and On-Chip Regulator
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• ID Locations
• In-Circuit Serial Programming™ (ICSP™)
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in
.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, the PIC18F87K90 family of
devices has a Watchdog Timer, which is either perma-
nently enabled via the Configuration bits or software
controlled (if configured as disabled).
The inclusion of an internal RC (LF-INTOSC) oscillator
also provides the additional benefits of a Fail-Safe
Clock Monitor (FSCM) and Two-Speed Start-up. FSCM
provides for background monitoring of the peripheral
clock and automatic switchover in the event of its fail-
ure. Two-Speed Start-up enables code to be executed
almost immediately on start-up, while the primary clock
source completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, the PIC18F87K90 family of
devices has a Watchdog Timer, which is either perma-
nently enabled via the Configuration bits or software
controlled (if configured as disabled).
The inclusion of an internal RC (LF-INTOSC) oscillator
also provides the additional benefits of a Fail-Safe
Clock Monitor (FSCM) and Two-Speed Start-up. FSCM
provides for background monitoring of the peripheral
clock and automatic switchover in the event of its fail-
ure. Two-Speed Start-up enables code to be executed
almost immediately on start-up, while the primary clock
source completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
28.1
Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location, 300000h.
The user will note that address, 300000h, is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh),
which can only be accessed using table reads and
table writes.
Software programming the Configuration registers is
done in a manner similar to programming the Flash
memory. The WR bit in the EECON1 register starts a
self-timed write to the Configuration register. In normal
operation mode, a TBLWT instruction, with the TBLPTR
pointing to the Configuration register, sets up the
address and the data for the Configuration register write.
Setting the WR bit starts a long write to the Configuration
register. The Configuration registers are written a byte at
a time. To write or erase a configuration cell, a TBLWT
instruction can write a ‘1’ or a ‘0’ into the cell. For
additional details on Flash programming, refer to
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location, 300000h.
The user will note that address, 300000h, is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh),
which can only be accessed using table reads and
table writes.
Software programming the Configuration registers is
done in a manner similar to programming the Flash
memory. The WR bit in the EECON1 register starts a
self-timed write to the Configuration register. In normal
operation mode, a TBLWT instruction, with the TBLPTR
pointing to the Configuration register, sets up the
address and the data for the Configuration register write.
Setting the WR bit starts a long write to the Configuration
register. The Configuration registers are written a byte at
a time. To write or erase a configuration cell, a TBLWT
instruction can write a ‘1’ or a ‘0’ into the cell. For
additional details on Flash programming, refer to
.