Microchip Technology ARD00385 Data Sheet

 2009-2011 Microchip Technology Inc.

DS39957D-page 5

50 49

RE2

/L

CDBIAS3

/P2

B

/C

CP

1

0

   

RE3

/CO

M

0

/P3

C

/CCP9

/RE

F

O

 

RE4

/CO

M

1

/P3

B

/CCP8

 

RE5

/CO

M

2

/P1

C

/CCP7

 

RE6

/CO

M

3

/P1

B

/CCP6

 

RE7

/ECCP2

/S

EG

31

/P

2

A 

RD0

/S

EG

0/

CTPL

S 

V

DD

V

SS

RD1

/S

EG

1/

T

5CKI/T

7G

 

RD2

/S

EG

2 

RD3

/S

EG

3 

RD4

/S

EG

4/

SDO

2

 

RD5

/S

EG

5/

SDI2

/SDA2

 

RD6

/S

EG

6/

SCK2

/S

CL

2 

RD7

/S

EG

7/

SS2

 

RE1/LCDBIAS2/P2C
RE0/LCDBIAS1/P2D

RG0/ECCP3/P3A

RG1/TX2/CK2/AN19/C3OUT

RG2/RX2/DT2/AN18/C3INA

RG3/CCP4/AN17/P3D/C3INB

MCLR/RG5

V

SS

V

DDCORE

/V

CAP

RF7/AN5/SS1/SEG25

RF6/AN11/SEG24/C1INA

RF5/AN10/CV

REF

/SEG23/C1INB

RF4/AN9/SEG22/C2INA

RF3/AN8/SEG21/C2INB/CTMUI

RF2/AN7/C1OUT/SEG20

RB0/INT0/SEG30/FLTO
RB1/INT1/SEG8
RB2/INT2/SEG9/CTED1

RB3/INT3/SEG10/CTED2/P2A

RB4/KBI0/SEG11
RB5/KBI1/SEG29/T3CKI/T1G
RB6/KBI2/PGC
V

SS

OSC2/CLKO/RA6
OSC1/CLKI/RA7
V

DD

RB7/KBI3/PGD

RC4/SDI1/SDA1/SEG16
RC3/SCK1/SCL1/SEG17
RC2/ECCP1/P1A/SEG13

ENVREG

RF

1

/A

N

6/C2

OUT

/S

E

G

19

/CT

D

IN

AV

DD

AV

SS

RA3

/AN3

/V

RE

F

+

RA2

/AN2

/V

RE

F

-

RA

1

/AN1

/S

E

G

18

RA0

/A

N

0

/UL

PWU

V

SS

V

DD

RA4

/T

0CKI/

S

E

G

14

R

A

5/

A

N

4/T

1C

K

I/S

E

G

1

5/T

3G

/H

LV

D

IN

RC1

/SO

S

CI

/ECCP2

/P

2A

/S

E

G

3

2

RC0

/SOSCO

/SCL

KI

RC7

/R

X1

/D

T1

/SEG

2

8

RC6

/T

X1

/C

K1

/SEG

2

7

RC5/SDO1/SEG12

54 53 52 51

58 57 56 55

60 59

64 63 62 61

The ECCP2 pin placement depends on the CCP2MX Configuration bit setting.

Not available on the PIC18F65K90 and PIC18F85K90.

For the QFN package, it is recommended that the bottom pad be connected to V

SS

.

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2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
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31

27 28 29 30

32

38
37
36
35
34
33

40
39

48
47
46
45
44
43
42
41

RG0/ECCP3/P3A

RG4/SEG26/RTCC/T7CKI

/T5G/CCP5/AN16/P1D/C3INC