Microchip Technology ADM00423 Data Sheet

DS22285A-page 14

© 2011 Microchip Technology Inc.

The EN input pin is a logic-level input used to enable or
disable the device. A logic high (> 2.2V) will enable the
regulator output, while a logic low (< 0.8V) will ensure
that the regulator is disabled. This pin is internally
pulled up to an internal reference and will be enabled
when V

IN

> UVLO, unless the EN pin is pulled low. The

maximum input voltage applied to the EN pin should
not exceed 6V.

This pin will provide the bootstrap voltage required for
driving the upper internal NMOS switch of the buck
regulator. An external ceramic capacitor placed
between the BOOST input pin and the SW pin will
provide the necessary drive voltage for the upper
switch. During steady state operation, the capacitor is
recharged on every low-side, synchronous switching
cycle. If the Switch mode approaches 100% duty cycle
for the high-side MOSFET, the device will automatically
reduce the duty cycle switch to a minimum off time of
240 ns on every 8

th

 cycle to recharge the boost

capacitor.

This is a separate ground connection used for the low-
side synchronous switch to isolate switching noise from
the rest of the device. 

There is no internal electrical connection between the
Exposed Thermal Pad (EP) and the P

GND

 and S

GND

pins. The EP must be connected to GND on the Printed
Circuit Board (PCB).