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Microchip Technology MA330019 Data Sheet

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dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
DS70291G-page  104
© 2007-2012 Microchip Technology Inc.
     
REGISTER 7-9:
IFS4: INTERRUPT FLAG STATUS REGISTER 4 
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
U-0
DAC1LIF
(2)
DAC1RIF
(2)
—
—
QEI2IF
FLTA2IF
PWM2IF
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
C1TXIF
(1)
DMA7IF
DMA6IF
CRCIF
U2EIF
U1EIF
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
DAC1LIF: DAC Left Channel Interrupt Flag Status bit
(2)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14
DAC1RIF: DAC Right Channel Interrupt Flag Status bit
(2)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13-12
Unimplemented: Read as ‘0’
bit 11
QEI2IF: QEI2 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10
FLTA2IF: PWM2 Fault A Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9
PWM2IF: PWM2 Error Interrupt Enable bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8-7
Unimplemented: Read as ‘0’
bit 6
C1TXIF: ECAN1 Transmit Data Request Interrupt Flag Status bit
(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5
DMA7IF: DMA Channel 7 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4
DMA6IF: DMA Channel 6 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3
CRCIF: CRC Generator Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2
U2EIF: UART2 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
U1EIF: UART1 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
Unimplemented: Read as ‘0’
 
Note 1: Interrupts are disabled on devices without an ECAN™ module.
2: Interrupts are disabled on devices without an Audio DAC module.