Microchip Technology MA330019 Data Sheet

DS70291G-page  130

© 2007-2012 Microchip Technology Inc.

7.6.1

INITIALIZATION

To configure an interrupt source at initialization:
1.

Set the NSTDIS bit (INTCON1<15>) if nested 
interrupts are not desired.

2.

Select the user-assigned priority level for the 
interrupt source by writing the control bits in the 
appropriate IPCx register. The priority level 
depends on the specific application and type of 
interrupt source. If multiple priority levels are not 
desired, the IPCx register control bits for all 
enabled interrupt sources can be programmed 
to the same non-zero value.

3.

Clear the interrupt flag status bit associated with 
the peripheral in the associated IFSx register.

4.

Enable the interrupt source by setting the 
interrupt enable control bit associated with the 
source in the appropriate IECx register.

7.6.2

INTERRUPT SERVICE ROUTINE

The method used to declare an ISR and initialize the 
IVT with the correct vector address depends on the 
programming language (C or assembler) and the 
language development tool suite used to develop the 
application. 
In general, the user application must clear the interrupt 
flag in the appropriate IFSx register for the source of 
interrupt that the ISR handles. Otherwise, the program 
re-enters the ISR immediately after exiting the routine. 
If the ISR is coded in assembly language, it must be 
terminated using a RETFIE instruction to unstack the 
saved PC value, SRL value and old CPU priority level.

7.6.3

TRAP SERVICE ROUTINE

A Trap Service Routine (TSR) is coded like an ISR, 
except that the appropriate trap status flag in the 
INTCON1 register must be cleared to avoid re-entry 
into the TSR.

7.6.4

INTERRUPT DISABLE

All user interrupts can be disabled using this 
procedure:
1.

Push the current SR value onto the software 
stack using the PUSH instruction.

2.

Force the CPU to priority level 7 by inclusive 
ORing the value OEh with SRL.

To enable user interrupts, the POP instruction can be 
used to restore the previous SR value.

The  DISI instruction provides a convenient way to 
disable interrupts of priority levels 1-6 for a fixed period 
of time. Level 7 interrupt sources are not disabled by 
the DISI instruction.

At a device Reset, the IPCx registers are 
initialized such that all user interrupt 
sources are assigned to priority level 4.

Only user interrupts with a priority level of 
7 or lower can be disabled. Trap sources 
(level 8-level 15) cannot be disabled.