Microchip Technology MA330019 Data Sheet
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
DS70291G-page 20
© 2007-2012 Microchip Technology Inc.
TABLE 2-2:
RESONATOR RECOMMENDATIONS
2.7
Oscillator Value Conditions on
Device Start-up
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to less than or equal to 8 MHz for start-up with PLL
enabled to comply with device PLL start-up conditions.
This means that if the external oscillator frequency is
outside this range, the application must start-up in the
FRC mode first. The default PLL settings after a POR
with an oscillator frequency outside this range will
violate the device operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration word.
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to less than or equal to 8 MHz for start-up with PLL
enabled to comply with device PLL start-up conditions.
This means that if the external oscillator frequency is
outside this range, the application must start-up in the
FRC mode first. The default PLL settings after a POR
with an oscillator frequency outside this range will
violate the device operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration word.
2.8
Configuration of Analog and
Digital Pins During ICSP
Operations
Digital Pins During ICSP
Operations
If MPLAB ICD 3 or REAL ICE is selected as a debug-
ger, it automatically initializes all of the analog-to-digital
input pins (ANx) as “digital” pins, by setting all bits in the
AD1PCFGL register.
The bits in this register that correspond to the
analog-to-digital pins that are initialized by MPLAB ICD
3 or REAL ICE, must not be cleared by the user
application firmware; otherwise, communication errors
will result between the debugger and the device.
If your application needs to use certain analog-to-digital
pins as analog input pins during the debug session, the
user application must clear the corresponding bits in
the AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 3 or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the AD1PCFGL register. Automatic
initialization of this register is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all analog-to-digital pins being
recognized as analog input pins, resulting in the port
value being read as a logic ‘0’, which may affect user
application functionality.
ger, it automatically initializes all of the analog-to-digital
input pins (ANx) as “digital” pins, by setting all bits in the
AD1PCFGL register.
The bits in this register that correspond to the
analog-to-digital pins that are initialized by MPLAB ICD
3 or REAL ICE, must not be cleared by the user
application firmware; otherwise, communication errors
will result between the debugger and the device.
If your application needs to use certain analog-to-digital
pins as analog input pins during the debug session, the
user application must clear the corresponding bits in
the AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 3 or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the AD1PCFGL register. Automatic
initialization of this register is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all analog-to-digital pins being
recognized as analog input pins, resulting in the port
value being read as a logic ‘0’, which may affect user
application functionality.
2.9
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternatively, connect a 1k to 10k resistor between V
driven to a logic-low state.
Alternatively, connect a 1k to 10k resistor between V
SS
and the unused pin.
Part
Number
Vendor
Freq.
Load
Cap.
Package
Case
Frequency
Tolerance
Mounting
Type
Operating
Temperature
FCR4.0M5T
TDK Corp.
4 MHz
N/A
Radial
±0.5%
TH
-40°C to +85°C
FCR8.0M5
TDK Corp.
8 MHz
N/A
Radial
±0.5%
TH
-40°C to +85°C
HWZT-10.00MD
TDK Corp.
10 MHz
N/A
Radial
±0.5%
TH
-40°C to +85°C
HWZT-20.00MD
TDK Corp.
20 MHz
N/A
Radial
±0.5%
TH
-40°C to +85°C
Legend:
TH = Through Hole