Microchip Technology MA330013 Data Sheet
©
2007 Microchip Technology Inc.
Preliminary
DS70165E-page 135
dsPIC33F
7.0
DIRECT MEMORY ACCESS
(DMA)
(DMA)
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer),
and buffers or variables stored in RAM, with minimal
CPU intervention. The DMA controller can
automatically copy entire blocks of data without
requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA controller
uses a dedicated bus for data transfers and therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer),
and buffers or variables stored in RAM, with minimal
CPU intervention. The DMA controller can
automatically copy entire blocks of data without
requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA controller
uses a dedicated bus for data transfers and therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
The dsPIC33F peripherals that can utilize DMA are
listed in Table 7-1 along with their associated Interrupt
Request (IRQ) numbers.
listed in Table 7-1 along with their associated Interrupt
Request (IRQ) numbers.
TABLE 7-1:
PERIPHERALS WITH DMA
SUPPORT
SUPPORT
The DMA controller features eight identical data
transfer channels.
transfer channels.
Each channel has its own set of control and status
registers. Each DMA channel can be configured to
copy data either from buffers stored in dual port DMA
RAM to peripheral SFRs, or from peripheral SFRs to
buffers in DMA RAM.
registers. Each DMA channel can be configured to
copy data either from buffers stored in dual port DMA
RAM to peripheral SFRs, or from peripheral SFRs to
buffers in DMA RAM.
The DMA controller supports the following features:
• Word or byte sized data transfers.
• Transfers from peripheral to DMA RAM or DMA
RAM to peripheral.
• Indirect Addressing of DMA RAM locations with or
without automatic post-increment.
• Peripheral Indirect Addressing – In some periph-
erals, the DMA RAM read/write addresses may
be partially derived from the peripheral.
be partially derived from the peripheral.
• One-Shot Block Transfers – Terminating DMA
transfer after one block transfer.
• Continuous Block Transfers – Reloading DMA
RAM buffer start address after every block
transfer is complete.
transfer is complete.
• Ping-Pong Mode – Switching between two DMA
RAM start addresses between successive block
transfers, thereby filling two buffers alternately.
transfers, thereby filling two buffers alternately.
• Automatic or manual initiation of block transfers
• Each channel can select from 20 possible
sources of data sources or destinations.
For each DMA channel, a DMA interrupt request is
generated when a block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled.
generated when a block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled.
Note:
This data sheet summarizes the features
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
Peripheral
IRQ Number
INT0
0
Input Capture 1
1
Input Capture 2
5
Output Compare 1
2
Output Compare 2
6
Timer2
7
Timer3
8
SPI1
10
SPI2
33
UART1 Reception
11
UART1 Transmission
12
UART2 Reception
30
UART2 Transmission
31
ADC1
13
ADC2
21
DCI
60
ECAN1 Reception
34
ECAN1 Transmission
70
ECAN2 Reception
55
ECAN2 Transmission
71