Microchip Technology MA330013 Data Sheet
©
2007 Microchip Technology Inc.
Preliminary
DS70165E-page 141
dsPIC33F
REGISTER 7-2:
DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
FORCE
(1)
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
—
IRQSEL6
(2)
IRQSEL5
(2)
IRQSEL4
(2)
IRQSEL3
(2)
IRQSEL2
(2)
IRQSEL1
(2)
IRQSEL0
(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FORCE: Force DMA Transfer bit
(1)
1
= Force a single DMA transfer (Manual mode)
0
= Automatic DMA transfer initiation by DMA request
bit 14-7
Unimplemented: Read as ‘
0
’
bit 6-0
IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits
(2)
0000000
-
1111111
= DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ
Note 1:
The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced
DMA transfer is complete.
DMA transfer is complete.
2:
Please see Table 6-1 for a complete listing of IRQ numbers for all interrupt sources.