Microchip Technology MCP2515DM-PTPLS Data Sheet

 2003-2012 Microchip Technology Inc.

DS21801G-page 1

• Implements CAN V2.0B at 1 Mb/s:

- 0 – 8 byte length in the data field

- Standard and extended data and remote 

frames 

• Receive Buffers, Masks and Filters:

- Two receive buffers with prioritized message 

storage

- Six 29-bit filters

- Two  29-bit  masks

• Data Byte Filtering on the First Two Data Bytes 

(applies to standard data frames)

• Three Transmit Buffers with Prioritization and 

Abort Features

• High-Speed SPI Interface (10 MHz):

- SPI modes 0,0 and 1,1

• One-Shot mode Ensures Message Transmission 

is Attempted Only One Time

• Clock Out Pin with Programmable Prescaler:

- Can be used as a clock source for other 

device(s)

• Start-of-Frame (SOF) Signal is Available for 

Monitoring the SOF Signal:

- Can be used for time-slot-based protocols 

and/or bus diagnostics to detect early bus 
degradation

• Interrupt Output Pin with Selectable Enables

• Buffer Full Output Pins Configurable as:

- Interrupt output for each receive buffer

- General purpose output

• Request-to-Send (RTS) Input Pins Individually 

Configurable as:

- Control pins to request transmission for each 

transmit buffer

- General purpose inputs

• Low-Power CMOS Technology:

- Operates from 2.7V – 5.5V

- 5 mA active current (typical)

- 1 µA standby current (typical) (Sleep mode)

• Temperature Ranges Supported:

- Industrial (I): -40°C to +85°C

- Extended (E): -40°C to +125°C

Microchip Technology’s MCP2515 is a stand-alone
Controller Area Network (CAN) controller that
implements the CAN specification, version 2.0B. It is
capable of transmitting and receiving both standard
and extended data and remote frames. The MCP2515
has two acceptance masks and six acceptance filters
that are used to filter out unwanted messages, thereby
reducing the host MCU’s overhead. The MCP2515
interfaces with microcontrollers (MCUs) via an industry
standard Serial Peripheral Interface (SPI).

16

5

TXCAN

RXCAN

V

DD

RESET

CS

SO

1

2

3

4

18

17

16

15

SI

SCK

INT

RX0BF

14

13

12

11

RX1BF

10

OSC2

OSC1

CLKOUT/SOF

TX2RTS

5

6

7

8

Vss

9

TX0RTS

TX1RTS

TXCAN

RXCAN

TX0RTS

OSC1

CLKOUT/SOF

OSC2

CS

V

DD

RESET

SO

SCK
INT

SI

RX0BF
RX1BF

V

SS

TX1RTS

TX2RTS

NC

NC

13
12

1
2

3
4
5
6

7
8
9

20
19

18
17
16
15

14

11

10

2

NC

TX2RTS

TX0RTS

SO

SI

OS

C2

NC

OS

C1

GND

RX

1B

F

SCK

RX

CA

N

TX

C

A

N

V

DD

RE

S

E

T

TX1RTS

EP

20

1

19 18 17

3

4

14

13

12

11

6

7

8

9

21

10

15

CLKOUT

CS

INT

RX

0B

F

* Includes Exposed Thermal
 Pad (EP); see