Microchip Technology MA330027 Data Sheet

DS70616G-page 122

 2009-2012 Microchip Technology Inc.

4.4.1

PAGED MEMORY SCHEME

The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814  architecture extends
the available data space through a paging scheme,
which allows the available data space to be accessed
using MOV instructions in a linear fashion for pre- and
post-modified Effective Addresses (EA). The upper half
of Base Data Space address is used in conjunction with
the Data Space Page registers, the 10-Bit Read Page
register (DSRPAG) or the 9-Bit Write Page register
(DSWPAG), to form an Extended Data Space (EDS)
address or Program Space Visibility (PSV) address.
The Data Space Page registers are located in the SFR
space.

Construction of the EDS address is shown in 

When DSRPAG<9> = 0 and the base address bit,
EA<15> = 1, DSRPAG<8:0> is concatenated onto
EA<14:0> to form the 24-bit EDS read address.
Similarly, when the base address bit, EA<15> = 1,
DSWPAG<8:0> is concatenated onto EA<14:0> to form
the 24-bit EDS write address.

1

DSRPAG<8:0>

9 Bits

EA

15 Bits

Select

Byte

24-Bit EDS EA

Select

EA

(DSRPAG = Don't Care)

No EDS Access

Select

16-Bit DS EA

Byte

EA<15> = 0

DSRPAG

0

EA<15>

Note: DS read access when DSRPAG = 0x000 will force an address error trap.

= 1?

DSRPAG<9>

Y

N

Generate

PSV Address

0