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Microchip Technology MA330027 Data Sheet

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 2009-2012 Microchip Technology Inc.
DS70616G-page 309
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 16-15: SPHASE
x: 
PWMx SECONDARY PHASE SHIFT REGISTER
,
)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SPHASEx<15:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SPHASEx<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
SPHASEx<15:0>: Secondary Phase Offset bits for PWMxL Output Pin 
(used in Independent PWM mode only)
Note 1: If ITB (PWMCONx<9>) = 0, the following applies based on the mode of operation:
•    Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCON<11:10>) = 00, 01 or 
10), SPHASEx<15:0> = Not used.
•
True Independent Output mode (PMOD<1:0> (IOCON<11:10>) = 11), SPHASEx<15:0> = Phase 
shift value for PWMxL only.
2: If ITB (PWMCONx<9>) = 1, the following applies based on the mode of operation:
•    Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCON<11:10>) = 00, 01 or 
10), SPHASEx<15:0> = Not used.
•
True Independent Output mode (PMOD<1:0> (IOCON<11:10>) = 11), 
SPHASEx<15:0> = Independent time base period value for PWMxL only.