Microchip Technology MA330027 Data Sheet
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616G-page 414
2009-2012 Microchip Technology Inc.
FIGURE 23-1:
ADCx MODULE BLOCK DIAGRAM
S&H0
S&H1
AN0
ANy
(3)
AN1
V
REFL
CH0SB<4:0>
CH0NA CH0NB
+
-
AN0
AN3
AN3
CH123SA
AN9
V
REFL
CH123SB
CH123NA CH123NB
AN6
+
-
S&H2
AN1
AN4
CH123SA
AN10
V
REFL
CH123SB
CH123NA CH123NB
AN7
+
-
S&H3
AN2
AN5
CH123SA
AN11
V
REFL
CH123SB
CH123NA CH123NB
AN8
+
-
CH1
(2)
CH0
CH2
(2)
CH3
(2)
CH0SA<4:0>
Channel
Scan
CSCNA
Alternate
Note 1: V
REF
+, V
REF
- inputs can be multiplexed
with other analog inputs.
2: Channels 1, 2 and 3 are not applicable
for the 12-bit mode of operation.
3: For dsPIC33EPXXX(GP/MC/MU)806 and
PIC24EPXXXGP806 devices, y = 0-15
and 24-31; for ADC2, y = 15; for all others,
y = 32.
and 24-31; for ADC2, y = 15; for all others,
y = 32.
4: When ADDMAEN (ADxCON4<8>) = 1,
enabling DMA, only ADCxBUF0 is used.
Input Selection
V
REF
+
(1)
AV
DD
AV
SS
V
REF
-
(1)
VCFG<2:0>
ADCxBUF0
(4)
ADCxBUF1
(4)
ADCxBUF2
(4)
ADCxBUFF
(4)
ADCxBUFE
(4)
SAR ADC
V
REFH
V
REFL