Microchip Technology MA330027 Data Sheet
2009-2012 Microchip Technology Inc.
DS70616G-page 47
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
4.0
MEMORY ORGANIZATION
The device architecture features separate program and
data memory spaces and buses. This architecture also
allows the direct access of program memory from the
data space during code execution.
data memory spaces and buses. This architecture also
allows the direct access of program memory from the
data space during code execution.
4.1
Program Address Space
The device program address memory space is 4M
instructions. The space is addressable by a 24-bit
value derived either from the 23-bit PC during program
execution, or from table operation or data space
remapping as described in
instructions. The space is addressable by a 24-bit
value derived either from the 23-bit PC during program
execution, or from table operation or data space
remapping as described in
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The device program memory map is shown in
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The device program memory map is shown in
FIGURE 4-1:
PROGRAM MEMORY MAP FOR dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 DEVICES
PIC24EPXXX(GP/GU)810/814 DEVICES
(
Note:
This data sheet summarizes the features
of the dsPIC33EPXXX(GP/MC/MU)806/
810/814 and PIC24EPXXX(GP/GU)810/
814 families of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 4. “Program
Memory” (DS70613) of the “dsPIC33E/
PIC24E Family Reference Manual”, which
is available from the Microchip web site
(
of the dsPIC33EPXXX(GP/MC/MU)806/
810/814 and PIC24EPXXX(GP/GU)810/
814 families of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 4. “Program
Memory” (DS70613) of the “dsPIC33E/
PIC24E Family Reference Manual”, which
is available from the Microchip web site
(
www.microchip.com
).
0x000000
0x000002
0x000002
0x7FFFFE
0xF80000
0xF80012
0xF80014
0xF80012
0xF80014
0xFEFFFE
0xFF0000
0xFF0002
0xFF0002
0xF7FFFE
0x000004
0x7FFFFC
0x000200
0x0001FE
Co
nfi
gura
tion
Me
mory S
pace
U
ser
Memor
y
S
pace
Note 1:
Memory areas are not shown to scale.
2:
The Reset location is controlled by the Reset Target Vector Select bit, RSTPRI (FICD<2>). See
for more information.
Reset Address
(2)
Device Configuration
User Program
Flash Memory
(87552 instructions)
Registers
DEVID (2 Words)
Unimplemented
(Read ‘0’s)
GOTO Instruction
(2)
Reserved
Reserved
Interrupt Vector Table
dsPIC33EP256MU806/810/814 and
Reset Address
(2)
Device Configuration
User Program
Flash Memory
(175104 instructions)
Registers
DEVID (2 Words)
Unimplemented
(Read ‘0’s)
GOTO Instruction
(2)
Reserved
Reserved
Interrupt Vector Table
dsPIC33EP512(GP/MC/MU)806/810/814 and
0x055800
0x0557FE
0x02AC00
0x02ABFE
Reserved
Reserved
0xFFFFFE
0x7FFFFA
0x7FC000
Flash Memory
Auxiliary Program
PIC24EP256GU810/814
PIC24EP512(GP/GU)806/810/814
GOTO Instruction
(2)
Flash Memory
0x800000
Auxiliary Program
Reset Address
(2)
GOTO Instruction
(2)
Reset Address
(2)
Reserved
Reserved
Write Latch
Write Latch
0xF9FFFE
0xFA0000
0xFA0000
0xFA00FE
0xFA0100
Vector
Auxiliary Interrupt
Vector
Auxiliary Interrupt
0x7FFFF8
0x7FBFFE
Ge
nera
l S
egmen
t
A
u
xiliary Seg
m
ent