Microchip Technology DM164130-2 Data Sheet
2010-2012 Microchip Technology Inc.
DS41414D-page 145
PIC16(L)F1946/47
12.13 PORTF Registers
). Setting a TRISF bit (= 1) will make the
corresponding PORTF pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISF bit (= 0) will make the corresponding
PORTF pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
corresponding output driver in a High-Impedance mode).
Clearing a TRISF bit (= 0) will make the corresponding
PORTF pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
shows how to initialize an I/O port.
Reading the PORTF register (
) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATF).
The TRISF register (
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATF).
The TRISF register (
) controls the
PORTF pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISF register are maintained set when using
them as analog inputs. I/O pins configured as analog
inputs always read ‘0’.
used as analog inputs. The user should ensure the bits
in the TRISF register are maintained set when using
them as analog inputs. I/O pins configured as analog
inputs always read ‘0’.
12.13.1
ANSELF REGISTER
The ANSELF register (
) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELF bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELF bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Setting the appropriate ANSELF bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELF bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
12.13.2
PORTF FUNCTIONS AND OUTPUT
PRIORITIES
PRIORITIES
Each PORTF pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in
pins, their combined functions and their output priorities
are shown in
.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in the priority list.
control goes to the peripheral with the highest priority.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in the priority list.
Note:
The ANSELF register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
TABLE 12-13: PORTF OUTPUT PRIORITY
Pin Name
Function Priority
(1)
RF0
SEG41 (LCD)
RF0
RF0
RF1
C2OUT (Comparator)
SRNQ (SR Latch)
SEG19 (LCD)
RF1
SRNQ (SR Latch)
SEG19 (LCD)
RF1
RF2
C1OUT (Comparator)
SEG20 (LCD)
SRQ (SR Latch)
RF2
SEG20 (LCD)
SRQ (SR Latch)
RF2
RF3
SEG21 (LCD)
RF3
RF3
RF4
SEG22 (LCD)
RF4
RF4
RF5
DACOUT (DAC)
SEG23 (LCD)
RF5
SEG23 (LCD)
RF5
RF6
SEG24 (LCD)
RF6
RF6
RF7
SEG25 (LCD)
RF7
RF7
Note 1:
Priority listed from highest to lowest.