Microchip Technology DM164130-2 Data Sheet

DS41414D-page 172

 2010-2012 Microchip Technology Inc.

For the ADC to meet its specified accuracy, the charge
holding capacitor (C

HOLD

) must be allowed to fully

charge to the input channel voltage level. The Analog
Input model is shown in 

. The source

impedance (R

S

) and the internal sampling switch (R

SS

)

impedance directly affect the time required to charge
the capacitor C

HOLD

. The sampling switch (R

SS

)

impedance varies over the device voltage (V

DD

), refer

to 

.  As the

source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an A/D acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, 

 may be

used. This equation assumes that 1/2 LSb error is used
(1,024 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.



 0.05µs/°C











 ln(1/2047)

–

–

–















 1

–

–









=



 1

–

–









=

–

–













=

 5.0V V





0.05









10pF 1k

 7k 10k





4.88 10

4

–







ln

–

1.37µs