Microchip Technology MA300015 Data Sheet

Page of 236
© 2011 Microchip Technology Inc.
DS70150E-page 11
dsPIC30F6010A/6015
FIGURE 1-2:
dsPIC30F6015 BLOCK DIAGRAM
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
Power-up
Timer
Oscillator
Start-up Timer
POR/BOR
Reset
Watchdog
Timer
Instruction
Decode and
Control
OSC1/CLKI
MCLR
V
DD
, V
SS
AN4/QEA/IC7/CN6/RB4
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
Low-Voltage
Detect
 UART1,
SPI1,
Motor Control
 
PWM
Timing
Generation
CAN1
AN5/QEB/IC8/CN7/RB5
16
PCH    PCL
Program Counter
ALU<16>
16
Address Latch
Program Memory
(144 Kbytes)
Data Latch
24
24
24
24
X Data Bus
IR
I
2
C™
QEI
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
PCU
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
10-bit ADC
Timers
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
SS2/CN11/RG9
U2TX/CN18/RF5
EMUC3/SCK1/INT0/RF6
Input
Capture
Module
 
Output
 Compare
Module
EMUC1/SOSCO/T1CK/CN0/RC14
EMUD1/SOSCI/T4CK/CN1/RC13
 
PORTB
C1RX/RF0
C1TX/RF1
U1RX/SDI1/RF2
EMUD3/U1TX/SDO1/RF3
SCL/RG2
SDA/RG3
    PORTG
    PORTF
 PORTD
16
 16
 16
   16 x 16
W Reg Array
Divide
 Unit
    Engine
      DSP
   Decode
ROM Latch 
16
Y Data Bus
Effective Address
X RAGU
X WAGU
 Y AGU
AN0/V
REF
+/CN2/RB0
AN1/V
REF
-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
OSC2/CLKO/RC15
U2RX/CN17/RF4
AV
DD
, AV
SS
UART2
SPI2
 16
 16
16
16
 16
PORTC
 PORTE
16
16
 16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control 
Logic
Loop
Control
Logic
Data Latch
Data Latch
Y Data 
(4 Kbytes)
RAM
X Data 
(4 Kbytes)
RAM
Address
Latch
 
Address
Latch
Control Signals 
to Various Blocks
EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
OC4/RD3
OC5/IC5/CN13/RD4
OC7/CN15/RD6
OC8/UPDN/CN16/RD7
IC1/FLTA/INT1/RD8
IC2/FLTB/INT2/RD9
IC3/INT3/RD10
IC4/INT4/RD11
16
Data EEPROM
(4 Kbytes)
 16
OC6/IC6/CN14/RD5