Microchip Technology MA300015 Data Sheet
dsPIC30F6010A/6015
DS70150E-page 132
© 2011 Microchip Technology Inc.
19.5.6
TRANSMIT INTERRUPTS
Transmit interrupts can be divided into 2 major groups,
each including various conditions that generate
interrupts:
each including various conditions that generate
interrupts:
• Transmit Interrupt
At least one of the three transmit buffers is empty (not
scheduled) and can be loaded to schedule a message
for transmission. Reading the TXnIF flags will indicate
which transmit buffer is available and caused the
interrupt.
scheduled) and can be loaded to schedule a message
for transmission. Reading the TXnIF flags will indicate
which transmit buffer is available and caused the
interrupt.
• Transmit Error Interrupts
A transmission error interrupt will be indicated by the
ERRIF flag. This flag shows that an error condition
occurred. The source of the error can be determined by
checking the error flags in the CAN Interrupt STATUS
register, CiINTF. The flags in this register are related to
receive and transmit errors.
ERRIF flag. This flag shows that an error condition
occurred. The source of the error can be determined by
checking the error flags in the CAN Interrupt STATUS
register, CiINTF. The flags in this register are related to
receive and transmit errors.
• Transmitter Warning Interrupt
The TXWAR bit indicates that the Transmit Error Counter
has reached the CPU warning limit of 96.
has reached the CPU warning limit of 96.
• Transmitter Error Passive
The TXEP bit (CiINTF<12>) indicates that the Transmit
Error Counter has exceeded the Error Passive limit of
127 and the module has gone to Error Passive state.
Error Counter has exceeded the Error Passive limit of
127 and the module has gone to Error Passive state.
• Bus Off
The TXBO bit (CiINTF<13>) indicates that the Transmit
Error Counter has exceeded 255 and the module has
gone to Bus Off state.
Error Counter has exceeded 255 and the module has
gone to Bus Off state.
19.6
Baud Rate Setting
All nodes on any particular CAN bus must have the
same nominal bit rate. In order to set the baud rate, the
following parameters have to be initialized:
same nominal bit rate. In order to set the baud rate, the
following parameters have to be initialized:
• Synchronization jump width
• Baud rate prescaler
• Phase segments
• Length determination of Phase2 Seg
• Sample point
• Propagation segment bits
19.6.1
BIT TIMING
All controllers on the CAN bus must have the same baud
rate and bit length. However, different controllers are not
required to have the same master oscillator clock. At dif-
ferent clock frequencies of the individual controllers, the
baud rate has to be adjusted by adjusting the number of
time quanta in each segment.
rate and bit length. However, different controllers are not
required to have the same master oscillator clock. At dif-
ferent clock frequencies of the individual controllers, the
baud rate has to be adjusted by adjusting the number of
time quanta in each segment.
The Nominal Bit Time can be thought of as being
divided into separate non-overlapping time segments.
These segments are shown in
divided into separate non-overlapping time segments.
These segments are shown in
• Synchronization segment (Sync Seg)
• Propagation time segment (Prop Seg)
• Phase segment 1 (Phase1 Seg)
• Phase segment 2 (Phase2 Seg)
The time segments and also the nominal bit time are
made up of integer units of time called time quanta or
T
made up of integer units of time called time quanta or
T
Q
. By definition, the nominal bit time has a minimum
of 8 T
Q
and a maximum of 25 T
Q
. Also, by definition,
the minimum nominal bit time is 1
μsec, corresponding
to a maximum bit rate of 1 MHz.
FIGURE 19-2:
CAN BIT TIMING
Input Signal
Sync
Prop
Segment
Phase
Segment 1
Phase
Segment 2
Sync
Sample Point
T
Q