Microchip Technology MA300015 Data Sheet
© 2011 Microchip Technology Inc.
DS70150E-page 43
dsPIC30F6010A/6015
5.2
Reset Sequence
A Reset is not a true exception because the interrupt
controller is not involved in the Reset process. The pro-
cessor initializes its registers in response to a Reset
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory loca-
tion, immediately followed by the address target for the
GOTO
controller is not involved in the Reset process. The pro-
cessor initializes its registers in response to a Reset
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory loca-
tion, immediately followed by the address target for the
GOTO
instruction. The processor executes the GOTO to
the specified address and then begins operation at the
specified target (start) address.
specified target (start) address.
5.2.1
RESET SOURCES
There are 6 sources of error which will cause a device
Reset.
Reset.
• Watchdog Time-out:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
processor is no longer executing the correct flow
of code.
• Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an Address Pointer will cause a Reset.
an Address Pointer will cause a Reset.
• Illegal Instruction Trap:
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
• Brown-out Reset (BOR):
A momentary dip in the power supply to the
device has been detected which may result in
malfunction.
device has been detected which may result in
malfunction.
• Trap Lockout:
Occurrence of multiple trap conditions
simultaneously will cause a Reset.
simultaneously will cause a Reset.
5.3
Traps
Traps can be considered as non-maskable interrupts
indicating a software or hardware error, which adhere
to a predefined priority, as shown in
indicating a software or hardware error, which adhere
to a predefined priority, as shown in
. They
are intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.
erroneous operation during debug and when operating
within the application.
Note that many of these trap conditions can only be
detected when they occur. Consequently, the question-
able instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
detected when they occur. Consequently, the question-
able instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
There are 8 fixed priority levels for traps: Level 8
through Level 15, which means that IPL3 is always set
during processing of a trap.
through Level 15, which means that IPL3 is always set
during processing of a trap.
If the user is not currently executing a trap, and he sets
the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
5.3.1
TRAP SOURCES
The following traps are provided with increasing prior-
ity. However, since all traps can be nested, priority has
little effect.
ity. However, since all traps can be nested, priority has
little effect.
Math Error Trap:
The math error trap executes under the following four
circumstances:
circumstances:
1.
Should an attempt be made to divide by zero,
the divide operation will be aborted on a cycle
boundary and the trap taken.
the divide operation will be aborted on a cycle
boundary and the trap taken.
2.
If enabled, a math error trap will be taken when
an arithmetic operation on either Accumulator A
or B causes an overflow from bit 31 and the
Accumulator Guard bits are not utilized.
an arithmetic operation on either Accumulator A
or B causes an overflow from bit 31 and the
Accumulator Guard bits are not utilized.
3.
If enabled, a math error trap will be taken when
an arithmetic operation on either Accumulator A
or B causes a catastrophic overflow from bit 39
and all saturation is disabled.
an arithmetic operation on either Accumulator A
or B causes a catastrophic overflow from bit 39
and all saturation is disabled.
4.
If the shift amount specified in a shift instruction
is greater than the maximum allowed shift
amount, a trap will occur.
is greater than the maximum allowed shift
amount, a trap will occur.
Note:
If the user does not intend to take correc-
tive action in the event of a trap error
condition, these vectors must be loaded
with the address of a default handler that
simply contains the RESET instruction. If,
on the other hand, one of the vectors
containing an invalid address is called, an
address error trap is generated.
tive action in the event of a trap error
condition, these vectors must be loaded
with the address of a default handler that
simply contains the RESET instruction. If,
on the other hand, one of the vectors
containing an invalid address is called, an
address error trap is generated.