Microchip Technology MA300015 Data Sheet

DS70150E-page 66

© 2011 Microchip Technology Inc.

The 16-bit timer can be placed in the Gated Time
Accumulation mode. This mode allows the internal T

CY

to increment the respective timer when the gate input
signal (T1CK pin) is asserted high. Control bit TGATE
(T1CON<6>) must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source set to internal (TCS = 0).

When the CPU goes into the Idle mode, the timer will
stop incrementing, unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon
termination of the CPU Idle mode. 

The input clock (F

OSC

/4 or external clock) to the 16-bit

Timer has a prescale option of 1:1, 1:8, 1:64 and 1:256
selected by control bits, TCKPS<1:0> (T1CON<5:4>).
The prescaler counter is cleared when any of the
following occurs: 

• write to the TMR1 register

• clearing of the TON bit (T1CON<15>)

• device Reset such as POR and BOR

However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.

TMR1 is not cleared when T1CON is written. It is
cleared by writing to the TMR1 register. 

During CPU Sleep mode, the timer will operate if:

• The timer module is enabled (TON = 1) and 

• The timer clock source is selected as external 

(TCS = 1) and

• The TSYNC bit (T1CON<2>) is asserted to a logic 

‘0’, which defines the external clock source as 
asynchronous

When all three conditions are true, the timer will con-
tinue to count up to the period register and be reset to
0x0000.

When a match between the timer and the period regis-
ter occurs, an interrupt can be generated, if the
respective timer interrupt enable bit is asserted.

The 16-bit timer has the ability to generate an interrupt
on period match.  When the timer count matches the
period register, the T1IF bit is asserted and an interrupt
will be generated, if enabled. The T1IF bit must be
cleared in software. The Timer Interrupt Flag, T1IF, is
located in the IFS0 Control register in the interrupt
controller.

When the Gated Time Accumulation mode is enabled,
an interrupt will also be generated on the falling edge of
the gate signal (at the end of the accumulation cycle).

Enabling an interrupt is accomplished via the
respective Timer Interrupt Enable bit, T1IE. The Timer
Interrupt Enable bit is located in the IEC0 Control
register in the interrupt controller.

Timer1, when operating in Real-Time Clock (RTC)
mode, provides time-of-day and event time-stamping
capabilities. Key operational features of the RTC are:

• Operation from 32 kHz LP oscillator

• 8-bit prescaler

• Low power 

• Real-Time Clock interrupts

These Operating modes are determined by setting the
appropriate bit(s) in the T1CON Control register.

SOSCI

SOSCO

R

C1

 C2

32.768 kHz
XTAL

C1 = C2 = 18 pF; R = 100K