Microchip Technology MA300015 Data Sheet

DS70150E-page 94

© 2011 Microchip Technology Inc.

14.7.2

TIMER OPERATION DURING CPU 
IDLE MODE

When the CPU is placed in the Idle mode and the QEI
module is configured in the 16-bit Timer mode, the
16-bit timer will operate if the QEISIDL bit (QEI-
CON<13>) = 0. This bit defaults to a logic ‘0’ upon
executing POR and BOR. For halting the timer module
during the CPU Idle mode, QEISIDL should be set
to ‘1’.

If the QEISIDL bit is cleared, the timer will function
normally, as if the CPU Idle mode had not been
entered.

The Quadrature Encoder Interface has the ability to
generate an interrupt on occurrence of the following
events:

• Interrupt on 16-bit up/down position counter 

rollover/underflow

• Detection of qualified index pulse, or if CNTERR 

bit is set

• Timer period match event (overflow/underflow)

• Gate accumulation event

The QEI Interrupt Flag bit, QEIIF, is asserted upon
occurrence of any of the above events. The QEIIF bit
must be cleared in software. QEIIF is located in the
IFS2 STATUS register.

Enabling an interrupt is accomplished via the respec-
tive enable bit, QEIIE. The QEIIE bit is located in the
IEC2 Control register.