Microchip Technology AC244045 Data Sheet
PIC16F72X/PIC16LF72X
DS41341E-page 152
© 2009 Microchip Technology Inc.
16.1.2.8
Asynchronous Reception Set-up:
1.
Initialize the SPBRG register and the BRGH bit
to achieve the desired baud rate (refer to
Section 16.2 “AUSART Baud Rate Generator
(BRG)”).
to achieve the desired baud rate (refer to
Section 16.2 “AUSART Baud Rate Generator
(BRG)”).
2.
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
The SYNC bit must be clear for asynchronous
operation.
3.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
PIE1 register and the GIE and PEIE bits of the
INTCON register.
4.
If 9-bit reception is desired, set the RX9 bit.
5.
Enable reception by setting the CREN bit.
6.
The RCIF interrupt flag bit of the PIR1 register
will be set when a character is transferred from
the RSR to the receive buffer. An interrupt will be
generated if the RCIE bit of the PIE1 register
was also set.
will be set when a character is transferred from
the RSR to the receive buffer. An interrupt will be
generated if the RCIE bit of the PIE1 register
was also set.
7.
Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
and, if 9-bit data reception is enabled, the ninth
data bit.
8.
Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register.
from the receive buffer by reading the RCREG
register.
9.
If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
clearing the CREN receiver enable bit.
16.1.2.9
9-bit Address Detection Mode Set-up
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
To set up an Asynchronous Reception with Address
Detect Enable:
1.
Initialize the SPBRG register and the BRGH bit
to achieve the desired baud rate (refer to
Section 16.2 “AUSART Baud Rate Generator
(BRG)”).
to achieve the desired baud rate (refer to
Section 16.2 “AUSART Baud Rate Generator
(BRG)”).
2.
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
The SYNC bit must be clear for asynchronous
operation.
3.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
PIE1 register and the GIE and PEIE bits of the
INTCON register.
4.
Enable 9-bit reception by setting the RX9 bit.
5.
Enable address detection by setting the ADDEN
bit.
bit.
6.
Enable reception by setting the CREN bit.
7.
The RCIF interrupt flag bit of the PIR1 register
will be set when a character with the ninth bit set
is transferred from the RSR to the receive buffer.
An interrupt will be generated if the RCIE inter-
rupt enable bit of the PIE1 register was also set.
will be set when a character with the ninth bit set
is transferred from the RSR to the receive buffer.
An interrupt will be generated if the RCIE inter-
rupt enable bit of the PIE1 register was also set.
8.
Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
The ninth data bit will always be set.
9.
Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
receive buffer and generate interrupts.
FIGURE 16-5:
ASYNCHRONOUS RECEPTION
Start
bit
bit 7/8
bit 1
bit 0
bit 7/8
bit 0
Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RX/DT pin
Reg
Rcv Buffer Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
RCREG
Stop
bit
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
causing the OERR (overrun) bit to be set.