Microchip Technology AC244045 Data Sheet
PIC16F72X/PIC16LF72X
DS41341E-page 164
© 2009 Microchip Technology Inc.
16.3.2.3
AUSART Synchronous Slave
Reception
Reception
The operation of the Synchronous Master and Slave
modes is identical (Section 16.3.1.4 “Synchronous
Master Reception”), with the following exceptions:
modes is identical (Section 16.3.1.4 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
never Idle
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE interrupt enable bit
of the PIE1 register is set, the interrupt generated will
wake the device from Sleep and execute the next
instruction. If the GIE bit is also set, the program will
branch to the interrupt vector.
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE interrupt enable bit
of the PIE1 register is set, the interrupt generated will
wake the device from Sleep and execute the next
instruction. If the GIE bit is also set, the program will
branch to the interrupt vector.
16.3.2.4
Synchronous Slave Reception Set-
up:
up:
1.
Set the SYNC and SPEN bits and clear the
CSRC bit.
CSRC bit.
2.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
PIE1 register and the GIE and PEIE bits of the
INTCON register.
3.
If 9-bit reception is desired, set the RX9 bit.
4.
Verify address detection is disabled by clearing
the ADDEN bit of the RCSTA register.
the ADDEN bit of the RCSTA register.
5.
Set the CREN bit to enable reception.
6.
The RCIF bit of the PIR1 register will be set
when reception is complete. An interrupt will be
generated if the RCIE bit of the PIE1 register
was set.
when reception is complete. An interrupt will be
generated if the RCIE bit of the PIE1 register
was set.
7.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Significant bit from the RX9D bit of the RCSTA
register.
8.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
receive FIFO by reading the RCREG register.
9.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register.
either clearing the CREN bit of the RCSTA
register.
TABLE 16-9:
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
RCREG
AUSART Receive Data Register
0000 0000
0000 0000
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000X
0000 000X
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
Legend:
x
= unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.