Microchip Technology AC244045 Data Sheet
© 2009 Microchip Technology Inc.
DS41341E-page 175
PIC16F72X/PIC16LF72X
REGISTER 17-2:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (SPI MODE)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP: SPI Data Input Sample Phase bit
SPI Master mode:
1
1
= Input data sampled at end of data output time
0
= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
SMP must be cleared when SPI is used in Slave mode
bit 6
CKE: SPI Clock Edge Select bit
SPI mode, CKP = 0:
1
1
= Data stable on rising edge of SCK
0
= Data stable on falling edge of SCK
SPI mode, CKP = 1:
1
1
= Data stable on falling edge of SCK
0
= Data stable on rising edge of SCK
bit 5
D/A: Data/Address bit
Used in I
2
C mode only.
bit 4
P: Stop bit
Used in I
2
C mode only.
bit 3
S: Start bit
Used in I
2
C mode only.
bit 2
R/W: Read/Write Information bit
Used in I
2
C mode only.
bit 1
UA: Update Address bit
Used in I
2
C mode only.
bit 0
BF: Buffer Full Status bit
1
= Receive complete, SSPBUF is full
0
= Receive not complete, SSPBUF is empty